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- 1 Relating Interrupt Articles
- 2 Asynchronous?
- 3 how come this article does not contain a paragraph about 'IRR'
- 4 Multiprocessing?
- 5 Interrupt routine example
- 6 Sharing interrupt lines
- 7 Look out for possible copyright violations in this article
Relating Interrupt Articles
There are a number of interrupt articles that seem to have no direction and a large amount of redundant information. I'm trying to organize them as I track them down.
I figure the layout should be as given below. There should be a seperate page for each Main. Each page should have redundent content eliminated, instead links should be placed to the appropriate main page. Of course, each Main page should be expanded apon. This includes a good introduction, history, features, programming information, references, etc.
Feel free to add additional links to this collection.
Catagory: Category: Interrupts
- Main: Intel 8259
- Main: Intel APIC Architecture
- Main: STI (x86 instruction)
- Main: CLI (x86 instruction)
- Main: INT (x86 instruction)
- Redirects: X86-int
- Main: Programmable Interrupt Controller
- Redirects: Interrupt controller
- Main: Advanced Programmable Interrupt Controller
- Main: Maskable interrupt
- Redirects: Masked interrupt
- Main: Non-Maskable interrupt
- Main: Interprocessor Interrupt
- Disambig: IPI
- TODO: Interrupt request register, Interrupt mask register, In-Service register
- Main: Interrupt
- Main: Interrupt Descriptor Table
- Disambig: IDT
- Main: Interrupt vector
- Main: Interrupt handler
- Main: Interrupt Storm
- Redirects: Interrupt storm
- Main: Interrupt latency
- Redirects: Interrupt Latency
- Main: Livelock (computer science)
From article: "an interrupt is an asynchronous signal from hardware or software indicating the need for attention". The article later goes on to explain synchronous interrupts caused by software. I am not an expert on this but this appears to be an error. -- Bubbachuck 05:07, 28 October 2006 (UTC)
"Synchronous interrupts" aren't really interrupts. 22.214.171.124 13:48, 21 November 2006 (UTC)
Ashu on wiki 01:20, 12 December 2006 (UTC) An interrupt is understood by the processor only when it is checked for. So, if a processor checks for interrupts only after the execute cycle of an instruction, even an asynchronous interrupt cannot be understood at any other time. Software interrupts are more predicatble in the sense that they can be part of dry run of a program. On the other hand, interrupts caused by other hardware is completely unpredictable for the program.
- Whatever the source (software or hardware), an interrupt is always handled by the processor synchronously: before executing the next instruction pointed to by program counter (PC), if an interrupt has been signaled, then at the next clock cycle, the processor saves the current context and jumps to a special routine (generally in ROM) that manages any kind of interrupts (which generally consumes some clock cycles before the real processing occurs).
- Instructions are always executed on clock cycles (even for interruption processing). So asynchronous is not really the appropriate term; we should prefer software-triggered or hardware-triggered, but the consequent behavior is the same.
- Note also that due to this extra-processing, latency between the event and start of useful interrupt processing is never null (but is often negligible) and depends on the processor family. Teuxe (talk) 15:10, 18 September 2012 (UTC)
how come this article does not contain a paragraph about 'IRR'
IRR redirects here. but i can't find no explanation. --
- You probably meant Interrupt Request Register? This is an implementation-specific register that may not be general enough to be explained in this article. Presently IRR points to a disambiguation page with no reference to this Interrupt Request Register.
- IRR could be introduced as an example of register, if a general algorithm for interrupt processing is described in this article. Teuxe (talk) 15:19, 18 September 2012 (UTC)
- Each interrupt line is always routed to a single processor. You may see different interrupt lines be mapped to different processors (for various reasons), but never will two processors be interrupted by the same hardware line. Teuxe (talk) 15:23, 18 September 2012 (UTC)
Interrupt routine example
I propose for deletion the interrupt routine example (for PIC MCU) placed on the article. This example is messy, contains unrelated functionality, looks pretty odd and occupies about one third of content. I think that interrupt handler routines (and related functionality) are very platform dependent (and can be very easily found in reference documentation), so in this article we must concentrate on common aspects without examples. If nobody against - I will delete it in a week time. Pmod (talk) 20:04, 2 April 2010 (UTC)
Sharing interrupt lines
As currently described the article leaves an impression that there are severe problems in sharing interrupt lines. In present day architectures the problems have been well solved by interrupt controllers, which can quickly identify and prioritize the interrupt sources and which can be used by software interrupt servers to implement prioritized interrupt handling of any desired complexity. The plain wired-or architecture, which is behind the claims in the architecture, is quite obsolete except in simplest systems. (This is not to say that wired-or itself is obsolete, only in this context.) Even with properly implemented wired-or architecture the problem of multiple interrupt sources of different priorities can be solved by having masking at the generating end and by using software interrupt request queuing. The article should be changed and expanded to reflect the current state of art.Lauri.pirttiaho (talk) 15:08, 29 January 2011 (UTC)
Look out for possible copyright violations in this article
This article has been found to be edited by students of the Wikipedia:India Education Program project as part of their (still ongoing) course-work. Unfortunately, many of the edits in this program so far have been identified as plain copy-jobs from books and online resources and therefore had to be reverted. See the India Education Program talk page for details. In order to maintain the WP standards and policies, let's all have a careful eye on this and other related articles to ensure that no material violating copyrights remains in here. --Matthiaspaul (talk) 15:20, 30 October 2011 (UTC)