Talk:List of Intel CPU microarchitectures
|This is the talk page for discussing improvements to the List of Intel CPU microarchitectures article.|
|WikiProject Computing / Hardware||(Rated List-class)|
Isn't Westmere just a shrink?
I thought Westmere was only a 32nm shrink of Nehalem, in the same way that Penryn is a 45nm shrink of Merom/Conroe/Woodcrest. If that is the case, then surely it's not a proper CPU microarchitecture?
--Masud 15:17, 25 September 2007 (UTC)
- I made them seperate entries because although Penryn is a 45nm shrink of Merom/Conroe/Woodcrest, there are several changes made. There is more cache, improved power management, faster divisor, etc. Westmere will probably be similar in changes, so I listed it as a sperate uarch. If you don't like how I have it, maybe we could indent those two lines to show that they are improved versions of Core and Nehalem. Imperator3733 19:23, 25 September 2007 (UTC)
- I have two issues.
- Firstly, assuming we keep Westmere on the list, Penryn should also feature on the list. This is because they are both shrinks.
- Secondly, Intel's "tick-tock" strategy is about introducing a new μarch every two years, and moving to the next manufacturing process in between new architectures. Nehalem is very different from Core, with the QuickPath (formerly called CSI) technology, and interchangeable cores to feature on the same piece of silicon, and more, as I'm sure you know. Compare the difference between Nehalem and Core μarchs, and the difference between Penryn and Core. I can only assume that Westmere will feature incremental improvements to Nehalem in the same way that Penryn features incremental improvements to Core.
- My recommendation would be to keep Westmere on this page, indent it as you described, but not call it a microarchitecture, but just a shrink. Also, we should add Penryn to this page, also indented, and also describe it as a shrink. Of course, if there is any Intel documentation that describes Westmere as a separate μarch from Nehalem, then we should keep it as you have done it.
- --Masud 11:22, 26 September 2007 (UTC)
Intel Tick-Tock merge proposal
Someone proposed merging this article and Intel Tick-Tock. I just wanted to state my agreement for such and plans to carry such out in the future if there are is not a consensus against such a move. I believe the Tick-Tock is descriptive of Intel's committed cadence across a number of their more recent CPU microarchitectural and fabrication technology developments and as such makes sense to incorporate it as one or more section(s) within this article (an argument could be made to incorporate this into a list of their fabrication technologies as well but since there is no such article and it so far only applies to their CPU microarchitectures I believe this is currently the most appropriate place). It could further be generalized in to a general roadmap table including parts that have not been part of their tick-tock cadence. 126.96.36.199 (talk) 15:08, 23 July 2013 (UTC)
Indentation = shrink ("tock")?
See http://en.wikipedia.org/w/index.php?title=List_of_Intel_CPU_microarchitectures&diff=570526280&oldid=570517480 if it's a tock, please revert. "2-way coarse-grained multithreading per core (not simultaneous)" seems to be quite different. Can it still be the same microarchitecture? When is it a new one, if there are tweaks? Always? See also Pendium M and Enhanched Pentium M (take out indent?). Not only a shrink. But minor enhanchments? New instructions(? SSE3 and SSE2) can hardly be minor enhanchments as they imply "new"/enhanched microarchitecture? Maybe th "tock" always includes something more that a shrink? comp.arch (talk) 13:02, 28 August 2013 (UTC)
SO I have an Arrandale cpu in my laptop. By the Wiki article, its desktop counterpart is the Clarkdale. However, its nopwhere to be found on the list. Why is this?188.8.131.52 (talk) 13:24, 20 January 2015 (UTC)BeeCier