Talk:MIPS instruction set
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- 1 Influence on SPARC
- 2 Use in TiVo
- 3 Free MIPS64 Simulator
- 4 MIPS licensees: soft IP and hard IP
- 5 Missing JALR instruction?
- 6 CPU family section improvement (table)
- 7 move MIPS architecture to MIPS instruction set
- 8 The lw and sw instructions are both real and pseudo
- 9 Computer architecture courses in universities and technical schools often study the MIPS architecture.
Influence on SPARC
I'd like to question the influence on SPARC. There were three RISC designs very early, that were demonstrations of the technology.
- The IBM effort under John Cocke. This was virtually unknown outside IBM until much, much later, but may have been the inspiration for IBM projects including ROMP, Power, and PowerPC.
- The Berkeley RISC project. An academic project that was probably the main inspiration for SPARC.
- The Stanford project. An academic project that was definitely the main inspiration for the commercial MIPS RISC.
SPARC and (commercial) MIPS were developed at much the same time so it is unlikely that commercial MIPS had much influence on SPARC. The original Stanford chip was a bit older than SPARC, and the SPARC people were certainly aware of it, but in looking at the major differences between Stanford and Berkeley RISC (sliding register window only in Berkeley, and not much else) SPARC follows the Berkeley model.
- Marice Wilkes states (in the foreword to Patterson/Hennessy) that MIPS is more-or-less the Stanford RISC project while SPARC is the commercialised Berkeley RISC. I therefore reformulated the sentence so that both are credited with influencing later RISCs. --Robbe
Use in TiVo
I believe the Series II TiVo's use MIPS and that's likely a high enough profile use to warrant a mention.
Free MIPS64 Simulator
Hello! I belong to a free (as in free speech) MIPS64 CPU Simulator development team. Do you think that it's acceptable to add the simulator's URL to the "External links" sections? The URL is http://www.edumips.org, the simulator's name is EduMIPS64. Thanks!
MIPS licensees: soft IP and hard IP
Missing JALR instruction?
Is the "MIPS assembly language" section missing the "jalr" instruction? From the SPIM (MIPS emulator) documentation "Jump and link register - jalr rs, rd - Unconditionally jump to the instruction whose address is in register rs. Save the address of the next instruction in register rd (which defaults to 31)." — Preceding unsigned comment added by 188.8.131.52 (talk) 21:44, 18 June 2012 (UTC)
CPU family section improvement (table)
It would be nice to add a column that would detail the instructions width; an another for the supported ABI(s) (application binary interface); and a last one for the supported endianness. Adding a line for the VIPER MIPS32 CPU would be nice to.184.108.40.206 (talk) 17:08, 18 March 2013 (UTC)
move MIPS architecture to MIPS instruction set
The lw and sw instructions are both real and pseudo
Both lw and sw can be both real instructions or pseudo, depending on the operand. If referring to a 32 bit label address, lw and sw will expand into 2 instructions as below.
sw rn, label[31:0]
lui at, label[31:16] sw rn, label[15:0](at)
lw rn, label[31:0]
lui rn, label[31:16] lw rn, label[15:0](rn) — Preceding unsigned comment added by 220.127.116.11 (talk) 05:52, 27 May 2014 (UTC)
Computer architecture courses in universities and technical schools often study the MIPS architecture.
This sentence is in the lead section, but it doesn't get expanded in the main article (courses are only mentioned in the simulator section). The citation does not support the statement; it is just one course listing that happens to use MIPS. I don't dispute the statement, but we should structure it better and support it with secondary sources. --Nczempin (talk) 13:16, 5 December 2014 (UTC)