Talk:Open collector

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TTL Logic[edit]

I think that the use of open collector in TTL logic should be mentioned as one of the relevant applications

A picture would be nice too.[edit]

Link with Open Drain[edit]

I think this article might benefit from some connection with the entry on Open drain. See also the talk page for that article. Mystic Pixel 03:45, 24 October 2006 (UTC) n,n,n, —Preceding unsigned comment added by 80.86.129.22 (talk) 10:12, 6 May 2009 (UTC)

No definition provided[edit]

Article should provide a definition before jumping straight to applications. —Preceding unsigned comment added by 209.19.246.2 (talk) 15:01, 26 October 2007 (UTC)

Definition too restrictive[edit]

There's no reason to categorize the open-collector or open-drain as an output in only digital logic. I've added a plug to that hole in the two articles, but I don't know how to change the categorization or the description immediately following the subject. Python2k (talk) 16:39, 19 April 2008 (UTC)

Picture is simply wrong[edit]

I can't fix it right now, but I wanted to leave a note -- the current version of the picture in this article is simply wrong. The lead with the arrow represents the emitter (not the collector, as it's currently labeled!) Mystic Pixel 10:57, 4 December 2007 (UTC)

Thanks to Omegatron for the fix. Mystic Pixel (talk) 09:29, 15 January 2008 (UTC)


Another confusing picture[edit]

Active-low wired-OR / active-high wired-AND circuit using open-drain gates.

Please have a look at this images's caption, as used in the current version of this article.

On the image's page, the summary says:

"A logic bus with an external pull-up resistor. Note the * indicating open-collector/open-drain NAND gates."

So is this a wired-AND or wired-NAND? I find it confusing to talk about wired-AND as long as the outputs have the negating bubbles. --Abdull (talk) 23:08, 7 February 2010 (UTC)

The "wired-AND" portion of the circuit is the direct connection of the outputs of the two open-collector gates. Those gates in the example happen to be NAND gates, but they could be any gate. Although in chip design it is likely they'd be NANDs, for the sake of simplicity it might be less confusing if the example gates were different (e.g. an AND and an OR). Mesdale (talk) 15:07, 16 March 2012 (UTC)

Open drain / open collector is naturally inverting. "ON", or logic 1, is when the output is activated. That means that the output is connected to ground - and so, with a pull-up resistor, an AND acts like a NAND. It gets confusing, no? To get real AND values out of an open drain device you need to use the inverted version, so showing an open collector NAND gate gives the logical functionality of an AND gate. Ergo, an OC-NAND is the correct gate to show for AND logic. Majenko (talk) 21:47, 11 June 2014 (UTC)

Hyphen, or not?[edit]

Which is the preferred term, "open-collector" or "open collector"? — Preceding unsigned comment added by 80.254.148.99 (talk) 10:46, 11 December 2012 (UTC)

Reference link[edit]

Reference link is broken http://www.scsita.org/terms/SCSI_Overview.html — Preceding unsigned comment added by Rajeshm75 (talkcontribs) 06:08, 24 September 2013 (UTC)

Irrelevant information[edit]

In the MOSFET section: "Such weak pullups, often on the order of 100 kΩ, reduce power usage by keeping input signals from floating. External pullups are stronger (perhaps 3 kΩ) to reduce signal rise times (like with I²C) or to minimize noise (like on system RESET inputs)."

This talks about inputs, but the page is about outputs. Should it really be there? Majenko (talk) 21:38, 11 June 2014 (UTC)