|This is the talk page for discussing improvements to the SPARC article.|
|WikiProject Computing / Hardware||(Rated C-class, High-importance)|
- 1 Inaccurate, false, incomplete
- 2 Solaris "designed for SPARC" ?
- 3 Ross Technology
- 4 Tagged Instructions
- 5 Table of Processors
- 6 SPARC64 is not T1
- 7 Multi-core/multi-thread SPARC64
- 8 ERC32
- 9 Superscalar/In-order, etc ?
- 10 SPARCLite?
- 11 "UA" and "JPS1" ?
- 12 Categorization?
- 13 SPARC64 III
- 14 Chronological ordering of SPARC microprocessor specifications
- 15 SPARC clones
- 16 "SPARC"
- 17 Number of Register windows
Inaccurate, false, incomplete
1. The article doesn't distinguish between an instruction set architecture and a particular implementation of the architecture. SPARC is an ISA specification. and UltraSPARCs are particular implementations. You can design and manufacture SPARC compatible processors, but you can't do that with x86. That's why SPARC is called open.
- Please explain. AMD makes x86 compatible chips. What is it you're saying?—Preceding unsigned comment added by 220.127.116.11 (talk • contribs) 01:58, January 24, 2005
- I think it is that I, as an individual or small company, can go to SPARC International and pay for a license for the SPARC. There exists no agency to approach for such a license for x86. In addition, SPARC's licensing terms are incredibly open, not requiring big patent payoffs such as with MIPS or ARM. Downix —Preceding unsigned comment added by 18.104.22.168 (talk) 11:13, 25 August 2008 (UTC)
- There is no doubt that SPARC is an open instruction set architecture. The "price" of the SPARC instruction set architecture specification is for covering the cost of redistributing the material, not for the licensing of. Also, consider the fact that Intel tried very hard back in the day to stop other companies from developing x86 compatible implementations. As far as I know, Sun never went after other companies making SPARC implementations and back in the late 1980s and early 1990s, there were quite a few companies in the business of SPARC microprocessors. The mere fact that AMD makes x86 compatible processors is not an indication that x86 is open. Rilak (talk) 11:24, 25 August 2008 (UTC)
2. It's ridiculous to imply that the original design favored register window *instead of* pipelining since the first SPARC was pipelined. Ever wondered why the delay slot was invented in the first place ? To fill the pipeline bubble after the branch in the early RISC designs.
3. UltraSPARC series are not a "standard" but just particular implementations.
4. In v9, there are 32 double precision (64bit) floating point registers
- and half of them (16) can be used as 32 single precision floating point registers. These 32 double precision registers can be used as 16 quad precision registers also.—Preceding unsigned comment added by 22.214.171.124 (talk • contribs) 02:24September 10, 2004
5. There's 8 global registers which are always available but no mention of it - the article implies there's only 24 general purpose registers available.
6. If a delay slot makes coding awkward, try hand-coding IA-64.
7. The article was apparently written by some open source zealot, but obviously the zealot had no clue on processors like Leon which is a particular implementation of SPARC and is open source (as the core design VHDL is under GPL). Have you ever seen an x86 design under GPL ? No, since that's impossible unless Intel allows. That's why SPARC is an open architecture.
I'll try to write a fair and accurate article on SPARC if I have some time, but if there's anybody with enough time to do so, take a look at http://www3.sk.sympatico.ca/jbayko/cpu.html before writing anything to get some clue. —Preceding unsigned comment added by 126.96.36.199 (talk • contribs) 16:30, April 8, 2004
Solaris "designed for SPARC" ?
There's no mention of Ross Technology, which made the HyperSPARC processors and closed in 1998 . However, I'm unclear on whether they would have actually licensed SPARC from SPARC International, so I'm not sure how to add this. StuartBrady 15:37, 12 January 2006 (UTC)
- Ross were spun off from Cypress, who were the builders of the first full-custom SPARC processors (the 7C601, or whatever the number was), and who were "licensed" for SPARC before SI existed; presumably they inherited whatever "license" they had from Cypress. Guy Harris 18:37, 12 January 2006 (UTC)
Currently, the last paragraph under SPARC#Features is slightly incorrect.
- Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.
The tagged instructions were added for the sake of Smalltalk, Lisp and other dynamically-typed languages, but Urs Hölzle and David Ungar report little benefit, at least for the Self programming language (see Do object-oriented languages need special hardware support?, ECOOP 1995). So I suggest changing the second sentence to (say)
- They were added for the sake of dynamically-typed languages such as Smalltalk, Lisp and ML that might use a tagged integer format.
If anyone can point to a system which does gain some real benefit from those instructions, I'd love to know about it. (When I first read about TADDcc and TSUBcc, I thought they were a wonderful idea. When I read that paper I was quite suprised. It would greatly please me to find about that TADDcc & TSUBcc are useful after all.)
- —Chris Chittleborough 14:28, 20 March 2006 (UTC)
Table of Processors
The table which shows details about the SPACR Processor is quite unreadable, is there any tutorial which tell me to add another headings in the row so that it could be quite readable ?—Preceding unsigned comment added by Mmansoor (talk • contribs) 23:19, May 4, 2006
SPARC64 is not T1
- Where does the current version of the article (after my changes to make the article no longer refer to SPARC64 as "the latest multi-core processor of Sun") imply that? Guy Harris 18:59, 5 May 2006 (UTC)
- Well, it still said "It has eight cores with a clock speed of 1.2 GHz per core. Each core is capable of running four threads simultaneously." That's true of the UltraSPARC T1, but not of any SPARC64 processor, as far as I can tell. I've removed that sentence for now. --StuartBrady 23:14, 5 May 2006 (UTC)
The slide show from October 2005 at http://primeserver.fujitsu.com/primepower/event/report/pf-2005/pdf/mpf2005scr.pdf says that SPARC64 VI is intended to be dual-core with each core supporting two "strands". It doesn't indicate that any current SPARC64 is either multi-core or multi-threaded. Guy Harris 21:18, 5 May 2006 (UTC)
Superscalar/In-order, etc ?
The article doesn't even mention wether versions of Sparc are superscalar, our of order, in order, how wide, etc. I'd say that this is at least as important and interesting (if not more) as cache size.—Preceding unsigned comment added by 188.8.131.52 (talk • contribs) 12:09, October 25, 2006
- How wide is said by the revision (SPARC v7 + v8 are 32-bit, v9 is 64-bit). —Preceding unsigned comment added by 184.108.40.206 (talk) 14:58, 18 September 2008 (UTC)
What is SPARCLite? My Fujitsu MB86833 66MHz that lives inside of my laser appears to be one, judging from http://www.fujitsu.com/downloads/MICRO/fmal/gdc/DS-MB86291-e4311021.pdf, page 5. From http://www.sparc.org/chips.shtml, I see that it is V8 arch. Thanks. - MSTCrow 15:32, 11 February 2007 (UTC)
"UA" and "JPS1" ?
These appear as modifiers to V9 under "Architecture Version" in the specifications table. The positioning implies that "JPS1" is specific to SPARC64, and "UA" to CMT processors—but what are they? This would seem like a worthy addition to the article.
On a related subject, especially since there seem to be a flurry of recent edits around it: should the table show what version of VIS is present (if any) for each processor?--NapoliRoma (talk) 17:58, 12 December 2007 (UTC)
This article is currently a part of "Category:Lists of microprocessors", but it is not a "List of..."-type article, which is what all entries (except for this one) in the category contains. Should this article be removed from this category? Rilak (talk) 13:04, 25 October 2008 (UTC)
- Well spotted! Yes, this doesn't belong in that category. Letdorf (talk) 16:20, 25 October 2008 (UTC).
I have a HAL document (SPARC64 III Product Overview, 29 April 1999) which says, "SPARC64 III (also called SPARC64 GP)..." (Emphasis mine). The table in this article describes the SPARC64 GP as a 0.18 micron microprocessor, whereas the HAL document claims that the two names refers to the same design - a 0.25 micron chip. Am I missing something? Rilak (talk) 03:36, 10 March 2009 (UTC)
Chronological ordering of SPARC microprocessor specifications
- It's vaguely chronological, but with some clustering of related series of processors. If we go for strict chronology, perhaps we should consider breaking it up into sub tables to illustrate the broad families? (eg. something like V7, SuperSPARC, hyperSPARC, MicroSPARC, TurboSPARC, UltraSPARC, SPARC64, UltraSPARC T?). Letdorf (talk) 11:08, 4 May 2009 (UTC).
- Yes, I thought about listing the various V7 implementations, but there were a number of them, most were very similar, the IUs and FPUs were discrete chips and details like die size and transistor count are hard to come by. Two interesting implementations worth noting though were the Panasonic MN10501 KAP used by Solbourne and the Bipolar Integrated Technology B5000. I believe these were both V7-compliant. Letdorf (talk) 12:40, 4 May 2009 (UTC).
- My understanding is that the B5000 and MN10501 were not very popular. While information about the B5000 is easy to get (from the Hot Chips archive), the MN10501 doesn't seem to have been mentioned at all. The SPARC chip sets made by Cypress Semiconductor and LSI Logic were the most commonly used, so perhaps they should have higher priority. Fujitsu, Texas Instruments and Weitek also made SPARC V7 parts. I think it is possible to obtain information about most of them from archived news articles, for example, this article has a bit about the first SPARC. Rilak (talk) 06:16, 5 May 2009 (UTC)
- Another good reference is the Sun Hardware Reference which lists the CPUs used in older Sun systems. The B5000 and the KAP aren't notable for their popularity, but they were interesting for being an ECL implementation, and an early example of a SPARC-compatible chip developed without the participation of (indeed, in competition with) Sun, respectively. There's some mention of the KAP here and here, and I think this paper is about the KAP too. Letdorf (talk) 10:01, 5 May 2009 (UTC).
- Interesting links. I looked for the KAP a while ago and didn't think anything. In regards to the links, I don't think there is anything that isn't in the list of SPARC V7s from SPARC International. I haven't looked into them yet, except for the CY7C601 chip set. We need a draft page somewhere to work on this. Rilak (talk) 12:24, 5 May 2009 (UTC)
Hello, I have been looking on informations about various sparc vendors other than SUN, and the list of clones found at http://openbsd.org/sparc.html, for exemple, does not appear to be mentioned somewhere on wikipedia. Can anyone write something about it ? Is it worthwhile to include them in the History section ? Thank you, Comte0 (talk) 14:42, 21 July 2010 (UTC)
- More generally, maybe there should be a "SPARC-based systems" section, like in the DEC Alpha article (but hopefully with more citations), mentioning Sun, Solbourne, Tadpole, RDI, SPARCstation clone vendors, Cray (CS6400), Meiko etc? Letdorf (talk) 22:33, 21 July 2010 (UTC).
- I think we need to discuss the relevance of including information about vendors of systems using SPARC uPs in an article about the SPARC ISA. It concerns me that articles about ISAs are more about the implementations of the ISA, and where those implementations have been used, than the ISA itself. We need to consider just what constitutes as an ISA's history. In my view, the history of an ISA involves discussing the various versions of the ISA and what CPUs have implemented the ISA. I think it is irrelevant to have any more information than this. Usage of specific CPUs by vendors of note (to minimize cruft—look at ARM architecture for an example of where-ARM-has-been-used cruft) should be in an article about the relevant CPU, not the ISA—a system does not "use" an ISA, it uses a CPU that implements an ISA. Putting information about who used specific SPARC uPs in the articles about those uPs is possible, since Wikipedia has articles about most SPARC uPs. What do you guys think? Rilak (talk) 06:44, 22 July 2010 (UTC)
- The ARM architecture article says :
- This article says:
Number of Register windows
The article says that the number of register windows is in the range from 3 to 32 (including). This is wrong for SPARC V8 (and V7) as it is clearly allowed to have an implementation with only two register windows ( http://www.sparc.com/standards/V8.pdf ,section 2.1). As this is a article about the SPARC ISA in general und not one that is specific to V9, it is wrong and must be corrected. Or it must be noted that for V9 the specs says 3 to 32. — Preceding unsigned comment added by 220.127.116.11 (talk) 19:04, 4 May 2013 (UTC)