Talk:Zero instruction set computer
|WikiProject Computing / Hardware||(Rated Start-class, Mid-importance)|
A lot of the text on this page is directly cribbed from the first link http://www.lsmarketing.com/LSMFiles/9809-ai1.htm
The link is given, but the text is not attributed. It should be rewritten. Heck, it should be rewritten anyways; it's barely intelligible. Dyfrgi 18:07, 14 September 2006 (UTC)
I would be very grateful to the one, who changed the names of the ZISC contributors, to respect the truth. The Wikipedia Foundation has enough trouble today with the "experts issue" to add any. There is no place here for personal ego issues. The ZISC implementation, as far as micro electronics is concerned, has been invented by Dr. Tannhof, and this creation has been patented by him at IBM under his name. The fact that someone else helped Dr Tannhof in his work is not a valid reason to change the ZISC entry in here. Thank you. Didier_Morandi 13:46, 2 December 2007 (UTC)
Transport triggered architecture
Isn't this just a transport triggered architecture with the only operation being a compare? Sounds like someone's coining fancy names and patenting just a specific implementation of a TTA. .froth. (talk) 18:42, 18 June 2008 (UTC)
- As far as I can tell, the architecture that Kevin Dowd in 1989 called a ""ZISC" Zero Instruction Set Computer Architecture" is identical to a transport triggered architecture.
- However, the architecture currently described in this Zero Instruction Set Computer article sounds more like a content-addressable memory.
- How is this kind of ZISC different from a content-addressable memory ? --22.214.171.124 (talk) 13:29, 20 October 2008 (UTC)
- I worked, though only a few days, on a ZISC chip mounted on a PC board, lent by the IBM Corbeil-Essonnes lab to the IBM ECAM (European Center of Applied Mathematics) in Paris, France, around 1995. I see absolutely no relationship between it and a content addressable memory. I would rather see it as an hardware implementation of a environment designed to host a Kohonen network. It was pretty good at making a classifying job, and you could for instance "teach" him to drive a simulated car on a smilated circuit (on the PC screen) in a matter of minutes, on the basis of : "If the pattern you see is this, do that; if you do not know, ask and incorporate it in your pattern => action set; if not answered, compare it to the patterns you now, determine the distance of each and make a reasonable guess; if corrected, memorize the corrected action, and so on.
- The chip was efficient. Unfortunately, while we were doing a lot of classifying jobs for data mining and text mining, the department manager was not convinced we could immediately afford to change our methods and abandon all of our existing algorithms. The neuron network specialist of the department, Jean Fargues, also disappeared a few months later in tragic circumstances and so we never put the ZISC in production work. 126.96.36.199 (talk) 14:34, 18 February 2013 (UTC)