Berkeley IRAM project

From Wikipedia, the free encyclopedia
  (Redirected from The Berkeley IRAM Project)
Jump to: navigation, search

In a 1996–2004 research project in the Computer Science Division of the University of California, Berkeley, the Berkeley IRAM project explored computer architecture enabled by the wide bandwidth between memory and processor made possible when both are designed on the same integrated circuit (chip).[1] Since it was envisioned that such a chip would consist primarily of random-access memory (RAM), with a smaller part needed for the central processing unit (CPU), the research team used the term "Intelligent RAM" (or IRAM) to describe a chip with this architecture.[2][3] Like the J–Machine project at MIT, the primary objective of the research was to avoid the Von Neumann bottleneck which occurs when the connection between memory and CPU is a relatively narrow memory bus between separate integrated circuits.

Theory[edit]

Main article: computational RAM

With strong competitive pressures, the technology employed for each component of a computer system—principally CPU, memory, and offline storage—is typically selected to minimize the cost needed to attain a given level of performance. Though both microprocessor and memory are implemented as integrated circuits, the prevailing technology used for each differs; microprocessor technology optimizes speed and memory technology optimizes density. For this reason, the integration of memory and processor in the same chip has (for the most part) been limited to static random-access memory (SRAM), which may be implemented using circuit technology optimized for logic performance, rather than the denser and lower-cost dynamic random-access memory (DRAM), which is not. Microprocessor access to off-chip memory costs time and power, however, significantly limiting processor performance. For this reason computer architecture employing a hierarchy of memory systems has developed, in which static memory is integrated with the microprocessor for temporary, easily accessible storage (or cache) of data which is also retained off-chip in DRAM.[4] Since the on-chip cache memory is redundant, its presence adds to cost and power. The purpose of the IRAM research project was to find if (in some computing applications) a better trade-off between cost and performance could be achieved with an architecture in which DRAM was integrated on-chip with the processor, thus eliminating the need for a redundant static memory cache—even though the technology used was not optimum for DRAM implementation.

Contribution[edit]

While it is fair to say that Berkeley IRAM did not achieve the recognition that Berkeley RISC received, the IRAM project was nevertheless influential. Although initial IRAM proposals focused on trade-offs between CPU and DRAM, IRAM research came to concentrate on vector instruction sets. Its publications were early advocates of the incorporation of vector processing and vector instruction sets into microprocessors, and several commercial microprocessors, such as the Intel AVX, subsequently adopted vector processing instruction set extensions.

Notes[edit]

  1. ^ Project history. Retrieved 2011-03-30.
  2. ^ Patterson, et al. (1997) IEEE Micro, 17 (2), p. 34.
  3. ^ "Intelligent RAM (IRAM)". 
  4. ^ Hennesey & Patterson (2007) Ch. 5

References[edit]

  • Bowman, N., Cardwell, N., Kozyrakis, C., Romer, C., Wang, H. (1997). "Evaluation of existing architectures in IRAM systems" First Workshop on Mixing Logic and DRAM, 24th International Symposium on Computer Architecture
  • Hennessy, J. L. and Patterson, D. A. (2007) Computer Architecture: A Quantitative Approach, Fourth Edition, Elsevier.
  • Kozyrakis, C.E., Perissakis, S., Patterson, D., Anderson, T., Asanovic, K., Cardwell, N., Fromm, R., Golbus, J., Gribstad, B., Keeton, K., Thomas, R., Treuhaft, N., Yelick, K. (1997) "Scalable Processors in the Billion Transistor Era: IRAM" Computer 30 (9) pp. 75–78. [1] doi:10.1109/2.612252.
  • Kozyrakis, C.; Patterson, D. (1998). "A New Direction for Computer Architecture Research" Computer, 31 (11), pp. 24–32. [2] doi:10.1109/2.730733.
  • Kozyrakis, C.E., Patterson, D.A. (2003). "Scalable, vector processors for embedded systems" IEEE Micro '23 (6) p. 36. doi:10.1109/MM.2003.1261385.
  • Patterson, D. (1995). "Microprocessors in 2020," The Solid-State Century: Scientific American Presents, pp. 62–67.
  • Patterson, D., Anderson, T., Cardwell, N., Fromm, R., Keeton, K., Kozyrakis, C., Thomas, R., and Yelick, K. (1997). "A Case for Intelligent RAM: IRAM," IEEE Micro, 17 (2), pp. 34–44. doi:10.1109/40.592312
  • Patterson, D., Asanovic, K., Brown, A., Fromm, R., Golbus, J., Gribstad, B., Keeton, K., Kozyrakis, C., Martin, D., Perissakis, S., Thomas, R., Treuhaft, N., Yelick, K. (1997). "Intelligent RAM (IRAM): the industrial setting, applications, and architectures" Proceedings 1997 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD '97), pp 2–7. [3] doi:10.1109/ICCD.1997.628842.

External links[edit]