Three-dimensional integrated circuit
In electronics, a three-dimensional integrated circuit (3D IC) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is pursuing this technology in many different forms, but it is not yet widely used; consequently, the definition is still somewhat fluid.
3D ICs vs. 3D packaging
3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into a single circuit. The chips in the package communicate using off-chip signaling, much as if they were mounted in separate packages on a normal circuit board.
Notable 3D chips
In 2004 Tezzaron Semiconductor built working 3D devices from six different designs. The chips were built in two layers with "via-first" tungsten TSVs for vertical interconnection. Two wafers were stacked face-to-face and bonded with a copper process. The top wafer was thinned and the two-wafer stack was then diced into chips. The first chip tested was a simple memory register, but the most notable of the set was an 8051 processor/memory stack that exhibited much higher speed and lower power consumption than an analogous 2D assembly.
In 2004, Intel presented a 3D version of the Pentium 4 CPU. The chip was manufactured with two dies using face-to-face stacking, which allowed a dense via structure. Backside TSVs are used for I/O and power supply. For the 3D floorplan, designers manually arranged functional blocks in each die aiming for power reduction and performance improvement. Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspots. The 3D design provides 15% performance improvement (due to eliminated pipeline stages) and 15% power saving (due to eliminated repeaters and reduced wiring) compared to the 2D Pentium 4.
The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory. Due to the high demand for memory bandwidth, a traditional I/O approach would consume 10 to 25 W. To improve upon that, Intel designers implemented a TSV-based memory bus. Each core is connected to one memory tile in the SRAM die with a link that provides 12 GB/s bandwidth, resulting in a total bandwidth of 1 TB/s while consuming only 2.2 W.
An academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students. The chip runs at a 1.4 GHz and it was designed for optimized vertical processing between the stacked chips which gives the 3D processor abilities that the traditional one layered chip could not reach. One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in harmony without any obstacles that would interfere with a piece of information traveling from one layer to another.
In ISSCC 2012, two 3D-IC-based multi-core designs using GlobalFoundries' 130 nm process and Tezzaron's FaStack technology were presented and demonstrated. 3D-MAPS, a 64 custom core implementation with two-logic-die stack was demonstrated by researchers from the School of Electrical and Computer Engineering at Georgia Institute of Technology. The second prototype was from the Department of Electrical Engineering and Computer Science at University of Michigan called Centip3De, a near-threshold design based on ARM Cortex-M3 cores.
As of 2008 there are four ways to build a 3D IC:
- Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias. A recent breakthrough overcame the process temperature limitation by partitioning the transistor fabrication to two phase. A high temperature phase which is done before layer transfer follow by a layer transfer use ion-cut, also known as layer transfer that has been the dominant method to produce SOI wafers for the past two decades. Multiple thin (10s–100s nanometer scale) layers of virtually defect free Silicon can be created by utilizing low temperature (<400C) bond and cleave techniques, and placed on top of active transistor circuitry. Follow by finalizing the transistors using etch and deposition processes. This monolithic 3D-IC technology has been researched at Stanford University under a DARPA-sponsored grant.
- Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These "through-silicon vias" (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad. Wafer-on-wafer bonding can reduce yields, since if any 1 of N chips in a 3D IC are defective, the entire 3D IC will be defective. Moreover, the wafers must be the same size, but many exotic materials (e.g. III-Vs) are manufactured on much smaller wafers than CMOS logic or DRAM (typically 300 mm), complicating heterogeneous integration.
- Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dice are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dice may be added to the stacks before dicing.
- Electronic components are built on multiple dice, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding. One advantage of die-on-die is that each component die can be tested first, so that one bad die does not ruin an entire stack. Moreover, each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance (e.g. matching multiple dice from the low power process corner for a mobile application).
Traditional scaling of semiconductor chips also improves signal propagation speed. However, scaling from current manufacturing and chip-design technologies has become more difficult, in part because of power-density constraints, and in part because interconnects do not become faster while transistors do. 3-D integrated circuits were invented to address the scaling challenge by stacking 2-D dies and connecting them in the 3rd dimension. This promises to speed up communication between layered chips, compared to planar layout. 3D ICs promise many significant benefits, including:
- More functionality fits into a small space. This extends Moore's law and enables a new generation of tiny but powerful devices.
- Partitioning a large chip into multiple smaller dies with 3D stacking can improve the yield and reduce the fabrication cost if individual dies are tested separately.
- Heterogeneous integration
- Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Moreover, components with incompatible manufacturing could be combined in a single 3D IC.
- Shorter interconnect
- The average wire length is reduced. Common figures reported by researchers are on the order of 10–15%, but this reduction mostly applies to longer interconnect, which may affect circuit delay by a greater amount. Given that 3D wires have much higher capacitance than conventional in-die wires, circuit delay may or may not improve.
- Keeping a signal on-chip can reduce its power consumption by 10–100 times. Shorter wires also reduce power consumption by producing less parasitic capacitance. Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.
- The vertical dimension adds a higher order of connectivity and offers new design possibilities.
- Circuit security
- The stacked structure complicates attempts to reverse engineer the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.
- 3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth buses between functional blocks in different layers. A typical example would be a processor+memory 3D stack, with the cache memory stacked on top of the processor. This arrangement allows a bus much wider than the typical 128 or 256 bits between the cache and processor. Wide buses in turn alleviate the memory wall problem.
Because this technology is new it carries new challenges, including:
- Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be commercially viable, defects could be repaired or tolerated, or defect density can be improved.
- Heat building up within the stack must be dissipated. This is an inevitable issue as electrical proximity correlates with thermal proximity. Specific thermal hotspots must be more carefully managed.
- Design complexity
- Taking full advantage of 3D integration requires sophisticated design techniques and new CAD tools.
- TSV-introduced overhead
- TSVs are large compared to gates and impact floorplans. At the 45 nm technology node, the area footprint of a 10μm x 10μm TSV is comparable to that of about 50 gates. Furthermore, manufacturability demands landing pads and keep-out zones which further increase TSV area footprint. Depending on the technology choices, TSVs block some subset of layout resources. Via-first TSVs are manufactured before metallization, thus occupy the device layer and result in placement obstacles. Via-last TSVs are manufactured after metallization and pass through the chip. Thus, they occupy both the device and metal layers, resulting in placement and routing obstacles. While the usage of TSVs is generally expected to reduce wirelength, this depends on the number of TSVs and their characteristics. Also, the granularity of inter-die partitioning impacts wirelength. It typically decreases for moderate (blocks with 20-100 modules) and coarse (block-level partitioning) granularities, but increases for fine (gate-level partitioning) granularities.
- To achieve high overall yield and reduce costs, separate testing of independent dies is essential. However, tight integration between adjacent active layers in 3D ICs entails a significant amount of interconnect between different sections of the same circuit module that were partitioned to different dies. Aside from the massive overhead introduced by required TSVs, sections of such a module, e.g., a multiplier, cannot be independently tested by conventional techniques. This particularly applies to timing-critical paths laid out in 3D.
- Lack of standards
- There are few standards for TSV-based 3D-IC design, manufacturing, and packaging, although this issue is being addressed. In addition, there are many integration options being explored such as via-last, via-first, via-middle; interposers or direct bonding; etc.
- Heterogeneous integration supply chain
- In heterogeneously integrated systems, the delay of one part from one of the different parts suppliers delays the delivery of the whole product, and so delays the revenue for each of the 3D-IC part suppliers.
- Lack of clearly defined ownership
- It is unclear who should own the 3D-IC integration and packaging/assembly. It could be assembly houses like ASE or the product OEMs.
Depending on partitioning granularity, different design styles can be distinguished. Gate-level integration faces multiple challenges and currently appears less practical than block-level integration.
- Gate-level integration
- This style partitions standard cells between multiple dies. It promises wirelength reduction and great flexibility. However, wirelength reduction may be undermined unless modules of certain minimal size are preserved. On the other hand, its adverse effects include the massive number of necessary TSVs for interconnects. This design style requires 3D place-and-route tools, which are unavailable yet. Also, partitioning a design block across multiple dies implies that it cannot be fully tested before die stacking. After die stacking (post-bond testing), a single failed die can render several good dies unusable, undermining yield. This style also amplifies the impact of process variation, especially inter-die variation. In fact, a 3D layout may yield more poorly than the same circuit laid out in 2D, contrary to the original promise of 3D IC integration. Furthermore, this design style requires to redesign available Intellectual Property, since existing IP blocks and EDA tools do not provision for 3D integration.
- Block-level integration
- This style assigns entire design blocks to separate dies. Design blocks subsume most of the netlist connectivity and are linked by a small number of global interconnects. Therefore, block-level integration promises to reduce TSV overhead. Sophisticated 3D systems combining heterogeneous dies require distinct manufacturing processes at different technology nodes for fast and low-power random logic, several memory types, analog and RF circuits, etc. Block-level integration, which allows separate and optimized manufacturing processes, thus appears crucial for 3D integration. Furthermore, this style might facilitate the transition from current 2D design towards 3D IC design. Basically, 3D-aware tools are only needed for partitioning and thermal analysis. Separate dies will be designed using (adapted) 2D tools and 2D blocks. This is motivated by the broad availability of reliable IP blocks. It is more convenient to use available 2D IP blocks and to place the mandatory TSVs in the unoccupied space between blocks instead of redesigning IP blocks and embedding TSVs. Design-for-testability structures are a key component of IP blocks and can therefore be used to facilitate testing for 3D ICs. Also, critical paths can be mostly embedded within 2D blocks, which limits the impact of TSV and inter-die variation on manufacturing yield. Finally, modern chip design often requires last-minute engineering changes. Restricting the impact of such changes to single dies is essential to limit cost.
IntSim is an open-source CAD tool to simulate 2D and 3D-ICs. It can be used for predicting 2D/3D chip power, die size, number of metal levels and optimal sizes of metal levels based on various technology and design parameters. Users can also study scaling trends, and use IntSim to optimize their chip designs.
HeatWave is a commercial CAD tool to simulate whole-chip temperature down to the device level. Inputs include layout data and power data]; outputs include a 3D thermal map and tabular temperature data suitable for annotating device-level temperature data into circuit simulators. HeatWave has been used by numerous 3D-IC research groups to accurately model temperature of test chips.
3DS (three dimensional stack) is a new IC packaging technology which uses the die stacking technique.
The digital electronics market requires a higher density semiconductor memory chip in order to cater to recently released CPU components, and the multiple die stacking technique has been suggested as a solution to this problem. JEDEC disclosed the upcoming DRAM technology includes the "3DS" die stacking plan at "Server Memory Forum", November 1–2, 2011, Santa Clara, CA.
3DS devices utilize Through-silicon via (TSV) technology for interconnect between dies. JEDEC is planning to start 3DS for current DDR3 for testing in advance of full production on DDR4.
- TSV connects die-die interconnection
- Master/Slave type architecture
- 1 Master die and 2, 4, or 8 Slave dies
- Master die isolate external connection and internal die-die connection
- Expanded memory capacity
- Load reduction ; Higher frequency
- Bus turn around time will reduce (Improved bus efficiency)
- Active termination power reduction ; Lower power consumption
- Higher cost
- Drill holes/Fill plug by metal/Put bumps
- 2 types of die (Master and Slave)
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