Through-silicon via

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In electronic engineering, a through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSVs are a high performance technique used to create 3D packages and 3D integrated circuits, compared to alternatives such as package-on-package, because the density of the vias is substantially higher, and because the length of the connections is shorter.

TSV technology in 3D packages[edit]

A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space and/or have greater connectivity. An alternate type of 3D package can be found in IBM's Silicon Carrier Packaging Technology, where ICs are not stacked but a carrier substrate containing TSVs is used to connect multiple ICs together in a package. In most 3D packages, the stacked chips are wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking).

TSV technology in 3D ICs[edit]

A 3D integrated circuit (3D IC) is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they behave as a single device. By using TSV technology, 3D ICs can pack a great deal of functionality into a small “footprint.” The different devices in the stack may be heterogeneous, e.g. combining CMOS logic, DRAM and III-V materials into a single IC. In addition, critical electrical paths through the device can be drastically shortened, leading to faster operation. The Wide I/O 3D DRAM memory standard (JEDEC JESD229) includes TSV in the design.[1]

History of the term "Through-Silicon Via"[edit]

The concept of Through-Silicon Via appeared in late 1990s. The co-founder and current CEO of ALLVIA, Inc. coined the term "through-silicon via" in 1997 as part of his original business plan. From the beginning, the vision of the business plan was to create a through silicon interconnect since these would offer significant performance improvements over wirebonds.

The article “Moore’s Law – The Z Dimension” was published in Solid State Technology magazine in January 2000. This article outlined the roadmap of the TSV development as a transition from 2.5-D chip stacking to wafer level stacking in the future. In one of the sections titled Through-Silicon Vias, Dr. Sergey Savastiouk wrote: “Investment in technologies that provide both wafer-level vertical miniaturization (wafer thinning) and preparation for vertical integration (through silicon vias) makes good sense.” He continued: “by removing the arbitrary 2-D conceptual barrier associated with Moore’s Law, we can open up a new dimension in ease of design, test, and manufacturing of IC packages. When we need it the most – for portable computing, memory cards, smart cards, cellular phones, and other uses – we can follow Moore’s Law into the Z dimension.” It was the first time the term "through-silicon via" was used in a technical publication.


  1. ^ Desjardins, Emily. "JEDEC Publishes Breakthrough Standard for Wide I/O Mobile DRAM". JEDEC. JEDEC. Retrieved 1 December 2014.