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Tiled rendering is the process of subdividing (or tiling) a computer graphics image by a regular grid in image space to exploit local spatial coherence in the scene and/or to facilitate the use of limited hardware rendering resources later in the graphics pipeline.
Tiled rendering is sometimes known as a "sort middle" architecture.
In a typical tiled renderer, geometry must first be transformed into screen space and assigned to screen-space tiles. This requires some storage for the lists of geometry for each tile. In early tiled systems, this was performed by the CPU, but all modern hardware contains hardware to accelerate this step. The list of geometry can also be sorted front to back, allowing the GPU to use hidden surface removal to avoid processing pixels that are hidden behind others, saving on memory bandwidth for unnecessary texture lookups. 
Once geometry is assigned to tiles, the GPU renders each tile separately to a small on-chip buffer of memory. This has the advantage that composition operations are cheap, both in terms of time and power. Once rendering is complete for a particular tile, the final pixel values for the whole tile are then written once to external memory. Also, since tiles can be rendered independently, the pixel processing lends itself very easily to parallel architectures with multiple tile rendering engines.
Tiles are typically small (16x16 and 32x32 pixels are popular tile sizes), although some architectures use much larger on-chip buffers and can be said to straddle the divide between tiled rendering and immediate mode ("sort last") rendering.
The Pixel Planes 5 project validated the tiled approach and invented a lot of the techniques now viewed as standard for tiled renderers. It is the work most widely cited by other papers in the field.
The tiled approach was also known early in the history of software rendering. Implementations of Reyes rendering often divide the image into "tile buckets".
Commercial Products – Desktop and Console
Early in the development of desktop GPUs, several companies developed tiled architectures. Over time, these were largely supplanted by immediate-mode GPUs with fast custom external memory systems.
Major examples of this are:
- PowerVR rendering architecture (1996): The rasterizer consisted of a 32×32 tile into which polygons were rasterized across the image across multiple pixels in parallel. On early PC versions, tiling was performed in the display driver running on the CPU. In the application of the Dreamcast console, tiling was performed by a piece of hardware. This facilitated deferred rendering—only the visible pixels were texture-mapped, saving shading calculations and texture-bandwidth.
- Microsoft Talisman (1996)
- Dreamcast (1998)
- Gigapixel GP-1 (1999)
- Xbox 360 (2005): the GPU contains an embedded 10 MiB framebuffer; this is not sufficient to hold the raster for an entire 1280×720 image with 4× anti-aliasing, so a tiling solution is superimposed when running in HD resolutions.
- Intel Larrabee GPU (2009) (canceled)
- PS Vita (2011) 
Commercial Products – Embedded
Due to the relatively low external memory bandwidth, and the modest amount of on-chip memory required, tiled rendering is a popular technology for embedded GPUs. Current examples include:
Vivante produces mobile GPUs which have tightly coupled frame buffer memory (similar to the Xbox 360 GPU described above). Although this can be used to render parts of the screen, the large size of the rendered regions means that they are not usually described as using a tile-based architecture.
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- "PowerVR: A Master Class in Graphics Technology and Optimization". Imagination Technologies. 2012-01-14. Retrieved 2014-01-11.
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- Mahaney, Jim (1998-06-22). "History". Pixel-Planes. University of North Carolina at Chapel Hill. Retrieved 2008-08-04.
- Fuchs, Henry (1989-07-01). "Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories". Pixel-Planes. ACM. Retrieved 2012-08-24.
- Smith, Tony (1999-10-06). "GigaPixel takes on 3dfx, S3, Nvidia with... tiles". Gigapixel. The Register. Retrieved 2012-08-24.
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