# Clock skew

(Redirected from Timing skew)

The operation of most digital circuit systems, such as computer systems, is synchronized by a "clock" that dictates the sequence and pacing of the devices on the circuit. Ideally, the input to each element has reached its final value before the next clock movement occurs so that the behaviour of the whole circuit can be predicted exactly. The maximum speed at which a system can run must account for the variance that occurs between the various elements of a circuit due to differences in physical composition, temperature, and path length.

In a synchronous circuit clock skew (TSkew) is the difference in the arrival time between two sequentially-adjacent registers. Given two sequentially-adjacent registers Ri and Rj with clock arrival times at register clock pins as TCi and TCj respectively, then clock skew can be defined as :

```                      TSkew i,j = TCi - TCj
```

Clock skew can be positive or negative. If the clock signals are in complete synchronicity, then the clock skew observed at these registers is zero.

## In circuit design

In circuit designs, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly.

There are two types of clock skew: negative skew and positive skew. Positive skew occurs when the transmitting register receives the clock earlier than the receiving register. Negative skew is the opposite: the receiving register gets the clock earlier than the sending register.

### Harmful skew

Two types of violation can be caused by clock skew. One problem is caused when the clock travels slower than the path from one register to another - allowing data to penetrate two registers in the same clock tick, or maybe destroying the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. Another problem is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period. Positive skew and negative skew cannot negatively impact setup and hold timing constraints respectively (see inequalities below).

### Beneficial skew

Clock skew can also benefit a circuit by increasing the clock period locally at which the circuit will operate correctly. For each source register and destination register connected by a path, the following inequalities must hold:

1. $T \ge reg + path_{max} + S - (s_d - s_s)$
2. $(s_d - s_s) \le reg + path_{min} - H$

where

• T is the clock period,
• reg is the source register's clock to Q delay,
• $path_{max}$ is the path with the longest delay from source to destination,
• S is the setup time of the destination register
• $path_{min}$ is the path with the shortest delay from source to destination,
• H is the hold time of the destination register,
• $(s_d - s_s)$ represents the clock skew from the source to the destination registers,
• $s_d$ is the clock skew to the destination register, and
• $s_s$ is the clock skew to the source register.

Positive clock skews are good for fixing setup violations, but can cause hold violations.

### Optimal skew

If the clock arrival times at individual registers are viewed as variables to be adjusted in order to minimize the clock period while satisfying the above inequalities for every path through the circuit, then the result is a Linear Programming problem.[1] In this linear program, zero clock skew is merely a feasible point - the solution to the linear program generally gives a clock period that is less than what is achieved by zero skew. In addition, safety margins greater than or equal to the zero skew case can be guaranteed by setting setup and hold times appropriately in the linear program.

Due to the simple form of this linear program, an easily programmed algorithm is available for arriving at a solution.[2]

Most CAD systems for VLSI and FPGA design contain facilities for optimizing clock skews.

## On a network

On a network such as the internet, clock skew describes the difference in time shown by the clocks at the different nodes on the network. It is usually an unavoidable phenomenon (at least if one looks at milli-second resolutions), but clock skew of tens of minutes or more is also quite common. Network operations that require time stamps which are comparable across hosts can be affected by clock skew. A number of protocols (e.g. Network Time Protocol) have been designed to reduce clock skew, and produce more stable functions. Some applications (such as game servers) may also use their own synchronization mechanism to avoid reliability problems due to clock skew.

## Interfaces

Clock skew is the reason why at fast speeds or long distances, serial interfaces (e.g. Serial Attached SCSI or USB) are preferred over parallel interfaces (e.g. parallel SCSI).