Unibus

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Unibus
Unibus
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Unibus backplane (left) and two printed circuit boards
Year created 1969
Created by Digital Equipment Corporation
Width in bits 18 address, 16 data

The Unibus was the earliest of several computer bus technologies used with PDP-11 and early VAX systems manufactured by the Digital Equipment Corporation (DEC) of Maynard, Massachusetts. The Unibus was developed around 1969 by Gordon Bell and student Harold McFarland while at Carnegie Mellon University.[1]

Technical specifications[edit]

A Unibus connector and extension cable

The Unibus was composed of 72 wires (2 connectors x 36 lines per connector). When not counting the power and ground lines, it is usually referred to as a 56 line bus. It could exist within a backplane or on a cable. Up to 20 nodes (devices) could be connected to a single Unibus segment; additional segments could be connected via a bus repeater.

The bus was completely asynchronous, allowing a mixture of fast and slow devices. It allowed the overlapping of arbitration (selection of the next bus master) while the current bus master was still performing data transfers. The 18 address lines allowed the addressing of a maximum of 256 KiB. Typically, the top 8 KiB was reserved for the registers of the memory-mapped I/O devices used in the PDP-11 architecture.

The design deliberately minimized the amount of redundant logic required in the system. For example, a system always contained more slave devices than master devices so most of the fancy logic required to implement asynchronous data transfers was forced into the relatively few master devices. For interrupts, only the interrupt-fielding processor needed to contain the complicated timing logic. The end result was that most I/O controllers could be implemented with very simple logic and most of the critical logic was implemented as a custom MSI IC.

Pinout[edit]

Number Name Type Description
18 A00-A17 1 Address Lines
16 D00-D15 1 Data Lines
4 BR4-BR7 1 Bus (Interrupt) Requests at priorities 4 (lowest) through 7 (highest)
4 BG4-BG7 2 Bus (Interrupt) Grants at priorities 4 (lowest) through 7 (highest)
1 NPR 1 Non Processor (DMA) Request
1 NPG 2 Non Processor (DMA) Grant
1 MSYNC 1 Master Sync
1 SSYNC 1 Slave Sync
1 BBSY 1 Bus Busy
1 SACK 1 Selection Acknowledge
1 INIT 1 Bus Init
1 INTR 1 Interrupt Request
1 PA 1 Parity control
1 PB 1 Parity control
2 C0-C1 1 Cyce Control Lines:
1 ACLO 3 AC Low
1 DCLO 3 DC Low
2 +5v - Power Lines (not counted as part of the 56)
14 Gnd - Ground Lines (not counted as part of the 56)
Unibus grant request continuity card

Type 1 lines are a normal multi-sender wired-OR bus with pullup resistors on each side of the bus, typically on a terminator card. Type 2 lines are selectively propagated by each card to the next slot -- if the card wants to keep the request grant it will assert the SACK line and not propagate the request to the next slot. If a slot is empty it is necessary to install a "grant continuity card" in the slot to propagate the signal to the next card. Type 3 signals are generated by the power supply and have only a single sender.[2]

The two control lines (C0 and C1) allowed the selection of four different data transfer cycles:

  • DATI (Data In, a read)
  • DATIP (Data In/Pause, the first portion of a Read-Modify-Write operation. A DATO or DATOB operation completes this.)
  • DATO (Data Out, a word write)
  • DATOB (Data Out/Byte, a byte write)
  • During an interrupt cycle, a fifth style of transfer was automatically invoked to convey an interrupt vector from the interrupting device to the interrupt-fielding processor.

References[edit]

  1. ^ Gardner Hendrie, Interviewer (June 23, 2005). "Bell (Gordon) Oral History". Reference number: X3202.2006. Computer History Museum. Retrieved May 20, 2011. 
  2. ^ Digital Equipment Corporation (1979). "Unibus Specification".