User:Dualdflipflop

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DualDFlipFlop is a name given to me by a long time ago, but never really used. Recently, having undergone much change, I decided it was time for a new handle for myself. The name is based on an Integrated Circuit explained below.

I had worked at a Radio Shack as a kid, after leaving, I still hung out with the friend of mine who had replaced me. While he was re-stocking the back wall, which had all the electronic components, he stumbled upon the 7474 and started laughing at the name "Dual D Flip-Flop" he said. When I asked why it was so funny, he told me this would be a perfect superhero name to go with his other one of the day "Orval Plax Knockoff". After that, he asked what it did, and so I tried to explain it to him, similar to how it is described below. After that, he and I called each other by those two names on occasion.

Quick digital flip-flop class:[edit]

First let's look at what a flip-flop is. In digital electronics the flip-flop or bistable multivibrator is a circuit capable of serving as a one-bit memory. The standard interface to a flip-flop includes zero, one, or two input signals; a clock signal; and an output signal. And since we are talking about the 7400 series Integrated Circuit, they also require power and ground connections. Some flip-flops include a clear input signal, which resets the current output, as is such with the 7474 Dual D type flip-flop.

Pulsing, otherwise known as "strobing" the clock causes the flip-flop to either change or retain its output signal, based upon the values of the input signals and the characteristic equation of the flip-flop. In this case Qnext = D (Not A Smiley Face)

The D ("delay") flip-flop takes one input, which it conveys to the output when the clock is strobed. Regardless of the current value of the output, it will assume a value 1 if D = 1 when the flip-flop is strobed or a value 0 if D = 0 when the flip-flop is strobed.

Also the D type flip-flop can also be seen as a "primitive delay" line or "zero-order hold", since the data is posted at the output one clock cycle after it arrives at the input.

Forgive me if that was too complex or I left something out. My mind is wondering today.

The corresponding truth table:[edit]

If all that confused you, perhaps this might help.

   ____________________
  |  D  |  Q  | Q next |
  |--------------------|
  |  0  |  X  |   0    |
  |-----|-----|--------|
  |  1  |  X  |   0    |
  |_____|_____|________|

D type flip-flop symbol:[edit]

The circuit symbol for a D-type flip-flop, where > is the clock input, D is the data input and Q is the stored data output.

   --------
  |        |
--|>       |
  |       Q|--
--|D       |
  |        |
   --------

The(7474) "Dual D Flip-Flop" Diagram:[edit]

If you would like to see under the hood of the IC, here is what it would look like. Now, some companies may change the label of the pinouts, but this is what the standard 7474 IC looks like. If you see something like 74xx74, xx being some letters like LS, HC, or whatever, that just means there is something different about the performance of the chip usually, however the function is still the same.

                                                       _
      Vcc    2CLR     2D      2CK     2PR     2Q      2Q
                                                            
     ----    ----    ----    ----    ----    ----    ----
  ---|14|----|13|----|12|----|11|----|10|----|09|----|08|---
  |--------------------------------------------------------|
  ||           |       |       |       |       |       |  ||
  ||           |       |       |       |--|    |--|    |  ||
  ||           |       |       |          o       |    |  ||
  ||           |       |       |      ..........  |    |  ||
  ||           |       |       |     :    PR    : |    |  ||
  ||           |       |-------^-----:D        Q:-|    |  ||
  ||           |               |     :          :      |  ||
  ||           |               |-----:>CK      _:      |  ||
  ||           |                     :         Q:------|  ||
  ||           |-----------------|   :    CLR   :         ||
  ||                             |   ............         ||
  ||  |------------|             |         1              ||
  ||  |            o             |---------|              ||
  ||  |      ............                                 ||
  ||  |      :    CLR  _:                                 ||
  ||  |      :         Q:---------------------|           ||
  ||  |   |--:>CK       :                     |           ||
  ||  |   |  :          :                     |           ||
  ||  | |-^--:D        Q:--------------|      |           ||
  ||  | | |  :    PR    :              |      |           ||
  ||  | | |  :..........:              |      |           ||
  ||  | | |       o                    |      |           ||
  ||  | | |-----| |------------|       |      |           ||
  ||  | |       |              |       |      |           ||
  ||  | |-----| |-----|        |       |      |           ||
  ||  |       |       |        |       |      |           ||
  |--------------------------------------------------------|
  ---|01|----|02|----|03|----|04|----|05|----|06|----|07|---
     ----    ----    ----    ----    ----    ----    ----   
                                               _            
     1CLR      1D      1CK     1PR     1Q     1Q      GND