VAX 9000

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The VAX 9000, code named Aridus or Aquarius, was a family of supercomputer and mainframe computers developed and manufactured by Digital Equipment Corporation (DEC) using processors implementing the VAX instruction set architecture (ISA). Aridus was a follow-on to the VAX 8800 family line.[1] The VAX 9000 code named Aquarius was positioned by Digital as its first mainframe.[2] In reality, it was Digital's second mainframe attempt, following their earlier and more successful 36-bit mainframe line (PDP-6 through DECSYSTEM-20) dating from the mid-1960s through early 1980s.[3] Initially, it was marketed as a supercomputer.[4] The VAX 9000 was introduced in October 1989[5] and faced problems such as the inability to ship large volumes.[6] It was designed to be water-cooled using the same plumbing as IBM mainframes and code-named Aquarius (“water-carrier”), but were first air-cooled[citation needed] Aridus (“dry”). The first models delivered were "field-upgradeable" to Aquarius as Model 210 follow-on but Digital officials thought nobody would require it, so they didn't offer it.[7]

Roughly four dozen systems were delivered before production was discontinued.[citation needed] Most sites ran the VMS operating system with a few sites choosing Ultrix.[citation needed] The pedigree of the vectorizing Fortran compiler is not clear. One representative example CPU sits in storage at the Computer History Museum (not on public display).

Models[edit]

VAX 9000 Model 110[edit]

The VAX 9000 Model 110 was an entry-level model with the same performance as the Model 210 but had a smaller memory capacity and was bundled with less software and services. On 22 February 1991, it was priced from US$920,000, and if fitted with a vector processor, from US$997,000.

VAX 9000 Model 210[edit]

The VAX 9000 Model 210 was an entry-level model with one CPU that could be upgraded. If a vector processor was present, it was known as the VAX 9000 Model 210VP.

VAX 9000 Model 4x0[edit]

The VAX 9000 Model 4x0 was a multiprocessor capable model, the value of "x" (1, 2, 3 or 4) denoting the number of CPUs present. These models supported the vector processor, with one vector processor supported per CPU. A maximal configuration had 512 MB of memory. The number of I/O buses supported varied, with the Model 410 and 420 supporting two XMI, ten CI and eight VAXBI; while the Model 430 and 440 supported four XMI, ten CI and 14 VAXBI.

Description[edit]

The VAX 9000 was a multiprocessor and supported one, two, three or four CPUs clocked at 62.5 MHz (16 ns cycle time). The system was based around a crossbar switch in the system control unit (SCU), to which the one to four CPUs, two memory controllers, two input/output (I/O) controllers and a service processor connected. I/O was provided by four Extended Memory Interconnect (XMI) buses.

Scalar processor[edit]

Each CPU was implemented with 13 Multi-Chip Units (MCUs), with each MCU containing several emitter-coupled logic (ECL) macrocell arrays which contained the CPU logic. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a bipolar process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.

Vector processor[edit]

The VAX 9000's CPU was coupled with a vector processor with a maximum theoretical performance of 125 MFLOPS. The vector processor circuitry was present in all units shipped and disabled via a software switch on units sold 'without' the vector processor. The vector processor was referred to as the V-box, and it was Digital's first ECL implementation of the VAX Vector Architecture. The design of the vector processor began in 1986, two years after development of the VAX 9000 CPU had begun.[8]

The V-box implementation comprised 25 Motorola Macrocell Array III (MCA3) devices spread over three multichip units (MCUs), which resided on the planar module. The V-box was optional and was field-installable. The V-box consisted of six subunits: the vector register unit, the vector add unit, vector multiply unit, vector mask unit, vector address unit and the vector control unit.

The vector register unit, also known as the vector register file, implemented the 16 vector registers defined by the VAX vector architecture. The vector register file was multi-ported and contained three write ports and five read ports. Each register consisted of 64 elements, and each element was 72 bits wide, with 64 bits used to store data and 8 bits used to store parity information.[9]


SID Scalar and Vector Processor Synthesis[edit]

SID (Synthesis of Integral Design) was a Logic synthesis program used to generate Logic gates for the VAX 9000. From high-level behavioral and Register-transfer level sources, approximately 93% of the CPU scalar and vector units, over 700,000 gates, were synthesized.[10]

SID was an Artificial intelligence Rule-based system and Expert system with over 1000 hand-written rules. In addition to Logic gate creation, SID took the design to the wiring level, allocating loads to nets and providing parameters for place and route CAD tools. As the program ran, it generated and expanded its own rule-base to 384,000 low-level rules.[11] [10] A complete synthesis run for the VAX 9000 took 3 hours.

Initially it was somewhat controversial, but was accepted in order to reduce the overall VAX 9000 project budget. Some engineers refused to use it. Others compared their own gate-level designs to those created by SID, eventually accepting SID for the gate-level design job. Since SID rules were written by expert logic designers and with input from the best designers on the team, excellent results were achieved. As the project progressed and new rules were written, SID-generated results became equal to or better than manual results for both area and timing. For example, SID produced a 64-bit adder that was faster than the manually-designed one. Manually-designed areas averaged 1 bug per 200 gates, whereas SID-generated logic averaged 1 bug per 20,000 gates. After finding a bug, SID rules were corrected, resulting in 0 bugs on subsequent runs.[10] The SID-generated portion of the VAX 9000 was completed 2 years ahead of schedule, whereas other areas of the VAX 9000 development encountered implementation problems, resulting in a much delayed product release. Following the VAX 9000, SID was never used again, and Digital Equipment Corporation never made another Mainframe computer. SID was granted 15 patents. [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26]

References[edit]

  1. ^ Computer & Communications Decisions. Hayden Publishing Company. 1988. 
  2. ^ Jane C. Blake, "Editor's Introduction", Digital Technical Journal, Volume 2, Number 4, Fall 1990.
  3. ^ Ceruzzi, Paul E. (2003). A History of Modern Computing. MIT Press. p. 341. ISBN 978-0-262-53203-7. "an environment of DEC mainframes like the PDP-10"
  4. ^ Semiconductor International. Cahners Publishing Company. 
  5. ^ DIGITAL Computing Timeline
  6. ^ John Markoff. "Market Place; Digital Finally Follows a Trend". The New York Times, 16 July 1990
  7. ^ Datamation. Cahners Publishing Company. 1992. 
  8. ^ Richard A. Brunner et al., "Vector Processing on the VAX 9000 System", Digital Technical Journal, Volume 2, Number 4, Fall 1990.
  9. ^ Dileep Bhandarkar and Richard Brunner, VAX Vector Architecture, Proc. 17th Annual Symposium on Computer Architecture (17th ISCA'90), Computer Architecture News (CAN), ACM SIGARCH, vol. 18, no. 2, Seattle, WA, June 1990, pp. 204–215.
  10. ^ a b c Carl S. Gibson, et al, VAX 9000 SERIES, Digital Technical Journal of Digital Equipment Corporation, Volume 2, Number 4, Fall 1990, pp118-129.
  11. ^ Donald F Hooper, SID: SYNTHESIS OF INTEGRAL DESIGN, International Conference on Computer Design: VLSI Processors 1988 ICCD, Proceedings of 1988 IEEE.
  12. ^ A3 EP patent 0259705 A3, Donald F Hooper, "Process for incorporating timing parameters in the synthesis of logic circuit design", issued 1988-03-16, assigned to Digital Equipment Corporation .
  13. ^ A3 EP patent 0259703 A3, Donald F Hooper & Snehamay Kundu, "Rule structure for insertion of new elements in a circuit design synthesis procedure", issued 1990-09-19, assigned to Digital Equipment Corporation .
  14. ^ A3 EP patent 0259702 A3, Donald F Hooper & Snehamay Kundu, "Rule structure in a procedure for synthesis of logic circuits", issued 1990-09-19, assigned to Digital Equipment Corporation .
  15. ^ A3 EP patent 0262397 A3, Donald F Hooper & Snehamay Kundu, "Procedure and data structure for synthesis and transformation of logic circuit designs", issued 1990-09-19, assigned to Digital Equipment Corporation .
  16. ^ A3 EP patent 0259704 A3, Donald F Hooper & Snehamay Kundu, "Bitwise implementation mechanism for a circuit design synthesis procedure", issued 1990-09-19, assigned to Digital Equipment Corporation .
  17. ^ A3 EP patent 0267379 A3, Donald F Hooper, "Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design", issued 1990-09-19, assigned to Digital Equipment Corporation .
  18. ^ US patent 5095441, Donald F Hooper; Edward G. Fortmiller & Snehamay Kundu et al., "Rule inference and localization during synthesis of logic circuit designs", issued 1992-03-10, assigned to Digital Equipment Corporation .
  19. ^ US patent 5150308, Donald F Hooper; Edward G. Fortmiller & David F. Wall, "Parameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designs", issued 1992-09-22, assigned to Digital Equipment Corporation .
  20. ^ US patent 5151867, Donald F Hooper; James L. Finnerty & David B. Fite et al., "Method of minimizing sum-of-product cases in a heterogeneous data base environment for circuit synthesis", issued 1992-09-29, assigned to Digital Equipment Corporation .
  21. ^ US patent 5175696, Donald F Hooper & Snehamay Kundu, "Rule structure in a procedure for synthesis of logic circuits", issued 1992-12-29, assigned to Digital Equipment Corporation .
  22. ^ US patent 5212650, Donald F Hooper & Snehamay Kundu, "Procedure and data structure for synthesis and transformation of logic circuit designs", issued 1993-05-18, assigned to Digital Equipment Corporation .
  23. ^ US patent 5222029, Donald F Hooper & Snehamay Kundu, "Bitwise implementation mechanism for a circuit design synthesis procedure", issued 1993-06-22, assigned to Digital Equipment Corporation .
  24. ^ A3 EP patent 0405728 A3, Donald F Hooper; Edward G. Fortmiller & Snehamay Kundu et al., "Rule inference and localization during synthesis of logic circuit designs", issued 1993-10-20, assigned to Digital Equipment Corporation .
  25. ^ US patent 5267175, Donald F Hooper, "Data base access mechanism for rules utilized by a synthesis procedure for logic circuit design", issued 1993-11-30, assigned to Digital Equipment Corporation .
  26. ^ US patent 5452226, Donald F Hooper & Snehamay Kundu, "Rule structure for insertion of new elements in a circuit design synthesis procedure", issued 1995-09-19, assigned to Digital Equipment Corporation .