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The VAX 9000, code named Aridus or Aquarius, was a family of Supercomputer and mainframe computers developed and manufactured by Digital Equipment Corporation (DEC) using processors implementing the VAX instruction set architecture (ISA). Aridus was thought as a follow-on the VAX 8800 family line. The VAX 9000 code named Aquarius was positioned by Digital as its first mainframe. In reality it was Digital's second mainframe attempt, following their earlier and more successful 36-bit mainframe line (PDP-6 through DECSYSTEM-20) dating from the mid-1960s through early 1980s. In the beginning was a supercomputer for high clock speeds. The VAX 9000 was introduced in October 1989 and faced problems such as the inability to ship large volumes. It was designed to be water-cooled using the same plumbing as IBM mainframes and code-named Aquarius (“water-carrier”), but were first air-cooled Aridus (“dry”). The first models delivered were "field-upgradeable" to Aquarius as Model 210 follow-on but Digital officials thought nobody will require it so didn't offered it.
Roughly four dozen systems were delivered before production was discontinued. Most sites ran the VMS operating system with a few sites choosing Ultrix. The pedigree of the vectorizing Fortran compiler is not clear.
VAX 9000 Model 110
The VAX 9000 Model 110 was an entry-level model with the same performance as the Model 210 but had a smaller memory capacity and was bundled with less software and services. On 22 February 1991, it was priced from US$920,000, and if fitted with a vector processor, from US$997,000.
VAX 9000 Model 210
The VAX 9000 Model 210 was an entry-level model with one CPU that could be upgraded. If a vector processor was present, it was known as the VAX 9000 Model 210VP.
VAX 9000 Model 4x0
The VAX 9000 Model 4x0 was a multiprocessor capable model, the value of "x" (1, 2, 3 or 4) denoting the number of CPUs present. These models supported the vector processor, with one vector processor supported per CPU. A maximal configuration had 512 MB of memory. The number of I/O buses supported varied, with the Model 410 and 420 supporting two XMI, ten CI and eight VAXBI; while the Model 430 and 440 supported four XMI, ten CI and 14 VAXBI.
The VAX 9000 was a multiprocessor and supported one, two, three or four CPUs clocked at 62.5 MHz (16 ns cycle time). The system was based around a crossbar switch in the system control unit (SCU), to which the one to four CPUs, two memory controllers, two input/output (I/O) controllers and a service processor connected. I/O was provided by four Extended Memory Interconnect (XMI) buses.
Each CPU was implemented with 13 Multi-Chip Units (MCUs), with each MCU containing several emitter-coupled logic (ECL) macrocell arrays which contained the CPU logic. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a bipolar process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.
The VAX 9000's CPU was coupled with a vector processor with a maximum theoretical performance of 125 MFLOPS. The vector processor circuitry was present in all units shipped and disabled via a software switch on units sold 'without' the vector processor. The vector processor was referred to as the V-box, and it was Digital's first ECL implementation of the VAX Vector Architecture. The design of the vector processor began in 1986, two years after development of the VAX 9000 CPU had begun.
The V-box implementation comprised 25 Motorola Macrocell Array III (MCA3) devices spread over three multichip units (MCUs), which resided on the planar module. The V-box was optional and was field-installable. The V-box consisted of six subunits: the vector register unit, the vector add unit, vector multiply unit, vector mask unit, vector address unit and the vector control unit.
The vector register unit, also known as the vector register file, implemented the 16 vector registers defined by the VAX vector architecture. The vector register file was multi-ported and contained three write ports and five read ports. Each register consisted of 64 elements, and each element was 72 bits wide, with 64 bits used to store data and 8 bits used to store parity information.
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