||It has been suggested that this article be merged into Intel APIC Architecture. (Discuss) Proposed since August 2013.|
The x2APIC architecture provides backward compatibility to the Intel APIC Architecture/xAPIC architecture (introduced with the Pentium/P6 and the Pentium 4 generations respectively) and forward extendability for future Intel platforms.
The major improvements of the x2apic concern the number of supported CPUs and performance of the interface.
The x2APIC now uses 32 bits to address CPUs, allowing to address up to 2^32-1 CPUs using the physical destination mode. The logical destination mode now works differently and introduces clusters. Using this mode, one can address up to 2^20-16 processors.
The improved interface reduces the number of needed APIC register access for sending Inter-processor interrupts.
More information on the Intel x2APIC Architecture can be found in the Intel 64 and IA-32 Architectures Software Developer's Manuals, Intel 64 Architecture x2APIC Specification, freely available on the Intel website.
- Intel APIC Architecture
- Intel 8259
- Advanced Programmable Interrupt Controller (APIC)
- Programmable Interrupt Controller (PIC)
- Inter-processor interrupt (IPI)
- Interrupt handler
- Message Signaled Interrupts (MSI)
- Non-maskable interrupt (NMI)
- Intel 64 Architecture x2APIC Specification (PDF)
- Intel MultiProcessor Specification Version 1.4 May 1997 (PDF)
- Intel 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC) Datasheet
- Key Benefits of the I/O APIC Microsoft's explanation of I/O APIC
- Importance of Implementing APIC-Based Interrupt Subsystems on Uniprocessor PCs
- Advanced Programmable Interrupt Controller A short introduction of what APIC is and its benefits