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Front-side bus

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A front-side bus (FSB) is a computer communication interface (bus) often used in Intel-chip-based computers during the 1990s and 2000s. The competing, and more general purpose, HyperTransport bus serves the same function for AMD CPUs. Both typically carry data between the central processing unit (CPU) and a memory controller hub, known as the northbridge.[1]

Depending on the implementation, some computers may also have a back-side bus that connects the CPU to the cache. This bus and the cache connected to it are faster than accessing the system memory (or RAM) via the front-side bus. The speed of the front side bus is often used as an important measure of the performance of a computer.

Within a multi-core processor, the back-side bus is often internal, with front-side bus for external communication

History

The term came into use by Intel Corporation about the time the Pentium Pro and Pentium II products were announced, in the 1990s.

"Front side" refers to the external interface from the processor to the rest of the computer system, as opposed to the back side, where the back-side bus connects the cache (and potentially other CPUs).[2]

A FSB is mostly used on PC-related motherboards (including personal computers and servers), seldom with the data and address buses used in embedded systems and similar small computers. This design represented a performance improvement over the single system bus designs of the previous decades, but sometimes is still called the "system bus".

Front-side buses usually connect the CPU and the rest of the hardware via a chipset, which Intel implemented as a northbridge and a southbridge. Other buses like the Peripheral Component Interconnect (PCI), Accelerated Graphics Port (AGP), and memory buses all connect to the chipset in order for data to flow between the connected devices. These secondary system buses usually run at speeds derived from the front-side bus clock, but are not necessarily synchronized to it.

In response to AMD's Torrenza initiative, Intel opened its FSB CPU socket to third party devices.[3] Prior to this announcement, made in Spring 2007 at Intel Developer Forum in Beijing, Intel had very closely guarded who had access to the FSB, only allowing Intel processors in the CPU socket. The first example was Field-programmable gate array (FPGA) co-processors, a result of collaboration between Intel-Xilinx-Nallatech[4] and Intel-Altera-XtremeData (which shipped in 2008).[5][6][7]

A typical chipset layout

CPU

The frequency at which a processor (CPU) operates is determined by applying a clock multiplier to the front-side bus (FSB) speed in some cases. For example, a processor running at 3200 MHz might be using a 400 MHz FSB. This means there is an internal clock multiplier setting (also called bus/core ratio) of 8. That is, the CPU is set to run at 8 times the frequency of the front-side bus: 400 MHz × 8 = 3200 MHz. By varying either the FSB or the multiplier, different CPU speeds can be achieved.

Memory

See also: Memory divider

Setting an FSB speed is related directly to the speed grade of memory a system must use. The memory bus connects the northbridge and RAM, just as the front-side bus connects the CPU and northbridge. Often, these two buses must operate at the same frequency. Increasing the front-side bus to 450 MHz in most cases also means running the memory at 450 MHz.

In newer systems, it is possible to see memory ratios of "4:5" and the like. The memory will run 5/4 times as fast as the FSB in this situation, meaning a 400 MHz bus can run with the memory at 500 MHz. This is often referred to as an 'asynchronous' system. It is important to realize that due to differences in CPU and system architecture, overall system performance can vary in unexpected ways with different FSB-to-memory ratios.

In image, audio, video, gaming, FPGA synthesis and scientific applications that perform a small amount of work on each element of a large data set, FSB speed becomes a major performance issue. A slow FSB will cause the CPU to spend significant amounts of time waiting for data to arrive from system memory. However, if the computations involving each element are more complex, the processor will spend longer performing these; therefore, the FSB will be able to keep pace because the rate at which the memory is accessed is reduced.

Peripheral buses

Similar to the memory bus, the PCI and AGP buses can also be run asynchronously from the front-side bus. In older systems, these buses are operated at a set fraction of the front-side bus frequency. This fraction was set by the BIOS. In newer systems, the PCI, AGP, and PCI Express peripheral buses often receive their own clock signals, which eliminates their dependence on the front-side bus for timing.

Overclocking

Main article: Overclocking

Overclocking is the practice of making computer components operate beyond their stock performance levels by manipulating the frequencies at which the component is set to run, and, when necessary, modifying the voltage sent to the component to allow it to operate at these higher frequencies more stably.

Many motherboards allow the user to manually set the clock multiplier and FSB settings by changing jumpers or BIOS settings. Almost all CPU manufacturers now "lock" a preset multiplier setting into the chip. It is possible to unlock some locked CPUs; for instance, some AMD Athlon processors can be unlocked by connecting electrical contacts across points on the CPU's surface. Some other processors from AMD and Intel are unlocked from the factory and labeled as an "enthusiast-grade" processors by end users and retailers because of this feature. For all processors, increasing the FSB speed can be done to boost processing speed by reducing latency between CPU and the northbridge.

This practice pushes components beyond their specifications and voltages may cause erratic behavior, overheating or premature failure. Even if the computer appears to run normally, problems may appear under a heavy load. Most PCs purchased from retailers or manufacturers, such as Hewlett-Packard or Dell, do not allow the user to change the multiplier or FSB settings due to the probability of erratic behavior or failure. Motherboards purchased separately to build a custom machine are more likely to allow the user to edit the multiplier and FSB settings in the PC's BIOS.

Evolution

The front-side bus had the advantage of high flexibility and low cost. Simple symmetric multiprocessors place a number of CPUs on an FSB, though performance does not scale linearly due to the architecture's bandwidth bottleneck.

The front-side bus was used in all of Intel's Atom, Celeron, Pentium, Core 2, and Xeon processor models through about 2008. Originally, this bus was a central connecting point for all system devices and the CPU. The speed of a faster CPU is wasted if it cannot fetch instructions and data as fast as it can execute them. The CPU must wait for one or more clock cycles until the memory returns its value, or access other devices attached to the FSB if it becomes a bottleneck.

The front-side bus was criticized by AMD as being an old and slow technology that limits system performance.[8] More modern designs use point-to-point connections like AMD's HyperTransport and Intel's QuickPath Interconnect (QPI).[9] FSB's fastest transfer speed was 1.6 GT/s, which provided only 80% of the theoretical bandwidth of a 16-bit HyperTransport 3.0 link as implemented on AM3 Phenom II CPUs, only half of the bandwidth of a 6.4 GT/s QuickPath Interconnect link, and only 25% of the bandwidth of a 32-bit HyperTransport 3.1 link. In addition, in an FSB-based architecture, the memory must be accessed via the FSB. In HT- and QPI-based systems, the memory is accessed independently by means of a memory controller on the CPU itself, freeing bandwidth on the HyperTransport or QPI link for other uses.

Transfer rates

The bandwidth or maximum theoretical throughput of the front-side bus is determined by the product of the width of its data path, its clock frequency (cycles per second) and the number of data transfers it performs per clock cycle. For example, a 64-bit (8-byte) wide FSB operating at a frequency of 100 MHz that performs 4 transfers per cycle has a bandwidth of 3200 megabytes per second (MB/s):

8 B × 100 MHz × 4/cycle = 3200 MB/s

The number of transfers per clock cycle depends on the technology used. For example, GTL+ performs 1 transfer/cycle, EV6 2 transfers/cycle, and AGTL+ 4 transfers/cycle. Intel calls the technique of four transfers per cycle Quad Pumping.

Many manufacturers publish the speed of the FSB in MHz, but often do not use the actual physical clock frequency but the theoretical effective data rate (which is commonly called megatransfers per second or MT/s). This is because the actual speed is determined by how many transfers can be performed by each clock cycle as well as by the clock frequency. For example, if a motherboard (or processor) has an FSB clocked at 200 MHz and performs 4 transfers per clock cycle, the FSB is rated at 800 MT/s.

Intel processors

CPU FSB Clock Number of Transfers/Cycle Bus Width Transfer Rate
Pentium 50 MHz-66 MHz 1 64-bit 400 MB/s-528 MB/s
Pentium Overdrive 25 MHz-66 MHz 1 64-bit 200 MB/s-528 MB/s
Pentium Pro 60 MHz-66 MHz 1 64-bit 480 MB/s-528 MB/s
Pentium MMX 60 MHz-66 MHz 1 64-bit 480 MB/s-528 MB/s
Pentium MMX Overdrive 50 MHz-66 MHz 1 64-bit 400 MB/s-528 MB/s
Pentium II 66 MHz-100 MHz 1 64-bit 528 MB/s-800 MB/s
Pentium II Xeon 100 MHz 1 64-bit 800 MB/s
Pentium II Overdrive 60 MHz-66 MHz 1 64-bit 480 MB/s-528 MB/s
Pentium III 100 MHz-133 MHz 1 64-bit 800 MB/s-1064 MB/s
Pentium III Xeon 100 MHz-133 MHz 1 64-bit 800 MB/s-1064 MB/s
Pentium III-M 100 MHz-133 MHz 1 64-bit 800 MB/s-1064 MB/s
Pentium 4 100 MHz-133 MHz 4 64-bit 3200 MB/s-4256 MB/s
Pentium 4-M 100 MHz 4 64-bit 3200 MB/s
Pentium 4 HT 133 MHz-200 MHz 4 64-bit 4256 MB/s-6400 MB/s
Pentium 4 HT Extreme Edition 200 MHz-266 MHz 4 64-bit 6400 MB/s-8512 MB/s
Pentium D 133 MHz-200 MHz 4 64-bit 4256 MB/s-6400 MB/s
Pentium Extreme Edition 200 MHz-266 MHz 4 64-bit 6400 MB/s-8512 MB/s
Pentium M 100 MHz-133 MHz 4 64-bit 3200 MB/s-4256 MB/s
Pentium Dual-Core 200 MHz-266 MHz 4 64-bit 6400 MB/s-8512 MB/s
Pentium Dual-Core Mobile 133 MHz-200 MHz 4 64-bit 6400 MB/s-8512 MB/s
Celeron 66 MHz-200 MHz 1-4 64-bit 528 MB/s-6400 MB/s
Celeron Mobile 133 MHz-200 MHz 1-4 64-bit 4256 MB/s-6400 MB/s
Celeron D 133 MHz 4 64-bit 4256 MB/s
Celeron M 66 MHz-200 MHz 1-4 64-bit 528 MB/s-6400 MB/s
Celeron Dual-Core 200 MHz 4 64-bit 6400 MB/s
Celeron Dual-Core Mobile 133 MHz-200 MHz 4 64-bit 4256 MB/s-6400 MB/s
Itanium 100 MHz-133 MHz 1 64-bit 800 MB/s-1064 MB/s
Itanium 2 100 MHz-166 MHz 4 64-bit 3200 MB/s-5312 MB/s
Xeon 100 MHz-400 MHz 4 64-bit 3200 MB/s-12800 MB/s
Core Solo 133 MHz-166 MHz 4 64-bit 4256 MB/s-5312 MB/s
Core Duo 133 MHz-166 MHz 4 64-bit 4256 MB/s-5312 MB/s
Core 2 Solo 133 MHz-200 MHz 4 64-bit 4256 MB/s-6400 MB/s
Core 2 Duo 200 MHz-333 MHz 4 64-bit 6400 MB/s-10656 MB/s
Core 2 Duo Mobile 133 MHz-266 MHz 4 64-bit 4256 MB/s-8512 MB/s
Core 2 Quad 266 MHz-333 MHz 4 64-bit 8512 MB/s-10656 MB/s
Core 2 Quad Mobile 266 MHz 4 64-bit 8512 MB/s
Core 2 Extreme 266 MHz-400 MHz 4 64-bit 8512 MB/s-12800 MB/s
Core 2 Extreme Mobile 200 MHz-266 MHz 4 64-bit 6400 MB/s-8512 MB/s
Atom 100 MHz-166 MHz 4 64-bit 3200 MB/s-5312 MB/s

AMD processors

CPU FSB Clock Number of Transfers/Cycle Bus Width Transfer Rate
K5 50 MHz-66 MHz 1 64-bit 400 MB/s-528 MB/s
K6 66 MHz 1 64-bit 528 MB/s
K6-II 66 MHz-100 MHz 1 64-bit 528 MB/s-800 MB/s
K6-III 66 MHz-100 MHz 1 64-bit 528 MB/s-800 MB/s
Athlon 100 MHz-133 MHz 2 64-bit 1600 MB/s-2128 MB/s
Athlon XP 100 MHz-200 MHz 2 64-bit 1600 MB/s-3200 MB/s
Athlon MP 100 MHz-133 MHz 2 64-bit 1600 MB/s-2128 MB/s
Mobile Athlon 4 100 MHz 2 64-bit 1600 MB/s
Athlon XP-M 100 MHz-133 MHz 2 64-bit 1600 MB/s-2128 MB/s
Duron 100 MHz-133 MHz 2 64-bit 1600 MB/s-2128 MB/s
Sempron 166 MHz-200 MHz 2 64-bit 2656 MB/s-3200 MB/s

See also

Wikimedia Commons has media related to Computer motherboards.

References

  1. ^ Scott Mueller (2003). Upgrading and repairing PCs (15th ed.). Que Publishing. p. 314. ISBN 978-0-7897-2974-3.
  2. ^ Todd Langley and Rob Kowalczyk (January 2009). "Introduction to Intel Architecture: The Basics" (PDF). "White paper". Intel Corporation. Retrieved May 28, 2011.
  3. ^ Charlie Demerjian (April 17, 2007). "Intel opens up its front side bus to the world+dog: IDF Spring 007 Xilinx heralds the bombshell". The Inquirer. Retrieved May 28, 2011.
  4. ^ "Nallatech™ Launches Early Access Program for the Industry's First FSB-FPGA Module". Business Wire news release. Nallatech. September 18, 2007. Retrieved June 14, 2011.
  5. ^ "XtremeData Offers Stratix III FPGA-Based Intel FSB Module". Business Wire news release. Chip Design magazine. September 18, 2007. Retrieved June 14, 2011.
  6. ^ Ashlee Vance (April 17, 2007). "High fiber diet gives Intel 'regularity' needed to beat AMD". The Register. Retrieved May 28, 2011.
  7. ^ "XtremeData Begins Shipping 1066 MHz Altera Stratix III FPGA-Based Intel FSB Module". Business Wire news release. XtremeData. June 17, 2008. Retrieved June 14, 2011.
  8. ^ Allan McNaughton (September 29, 2003). "AMD HyperTransport Bus: Transport Your Application to Hyper Performance". AMD.
  9. ^ "An Introduction to the Intel QuickPath Interconnect" (PDF). Intel Corporation. January 30, 2009. Retrieved June 14, 2011.
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