10 nanometer

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For the length in general and comparison, see 10 nanometres.

In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.

As of 2015 10nm devices are still under commercial development.



The ITRS' original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm. Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, claimed in 2008 that Intel saw a 'clear way' towards the 10 nm node.[1][2] At the 11 nm node, Intel expected (in 2006) to be using a half-pitch of around 21 nm, in 2015,[3] Nvidia's chief scientist, William Dally, claimed that they would also reach 11 nm semiconductors in 2015, a transition he claimed would be facilitated principally through new electronic design automation tools.[4]

This 10nm design rule is considered likely to be realized by multiple patterning,[5][6][7] given the difficulty of implementing EUV lithography by 2015.[8]

Potential technologies[edit]

While the roadmap has been based on the continuing extension of CMOS technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a monolayer or even less. Scientists have estimated that transistors at these dimensions are significantly affected by quantum tunnelling.[9] As a result, non-silicon extensions of CMOS, using III-V materials or Carbon nanotube/nanowires, as well as non-CMOS platforms, including molecular electronics, spin-based computing, and single-electron devices, have been proposed. Hence, this node marks the practical beginning of nanoelectronics.

The extensive use of ultra-low-k dielectrics (such as spin-on polymers or other porous materials) means that conventional photolithography, etch, or even chemical-mechanical polishing processes are unlikely to be used, because these materials contain a high density of voids and gaps. At the ~10 nm scale, quantum tunneling (especially through gaps) becomes a significant phenomenon.[10] Controlling gaps on these scales by means of electromigration can produce interesting electrical properties.[11]

Quantum tunneling may not be a disadvantage if its effect on device behavior can be understood, and exploited, in the design. Future transistors may have insulating channels. An electron wave function decays exponentially in a "classically forbidden" region at a rate that can be controlled by the gate voltage. Interference effects are also possible;[12] Alternate option is in heavier mass semiconducting channels.[13] Photoemission electron microscopy (PEEM) data has been used to show that low energy electrons ~1.35 eV could travel as far as ~15 nm in SiO2, despite an average measured attenuation length of 1.18 nm.[14]

Technology demos[edit]

On 15 November 2012, Samsung Electronics unveiled a 64 gigabyte (GB) embedded multimedia card (eMMC) based on 10 nm class process technology.[15]

In April 2015, TSMC announced that 10 nm production would begin at the end of 2016.[16]

On 23 May 2015, Samsung Electronics showed off a wafer of 10nm FinFET chips.[17]

Mass production[edit]

On 11 April 2013, Samsung announced that it was mass-producing High-Performance 128-gigabit 3-bit Multi-level-cell NAND Flash Memory with a technology somewhere between 10 nm and 20 nm.[18]


  1. ^ Damon Poeter. "Intel's Gelsinger Sees Clear Path To 10nm Chips". Archived from the original on 2009-06-22. Retrieved 2009-06-20. 
  2. ^ "MIT: Optical lithography good to 12 nanometers". Archived from the original on 2009-06-22. Retrieved 2009-06-20. 
  3. ^ Borodovsky, Y. (2006). "Marching to the beat of Moore's Law". Proc. SPIE 6153. doi:10.1117/12.655176. 
  4. ^ "Nvidia Chief Scientist: 11nm Graphics Chips with 5000 Stream Processors Due in 2015". XBit Labs. July 30, 2009. Archived from the original on 2009-09-03. Retrieved 2009-08-27. 
  5. ^ SEMICON West - Lithography Challenges and Solutions
  6. ^ J. Word et al., Proc. SPIE 6925 (2008).[full citation needed]
  7. ^ Intel extending ArF lithography
  8. ^ CNSE Technology Development Consortium for EUVL
  9. ^ "Intel scientists find wall for Moore's Law". ZDNet. December 1, 2003. 
  10. ^ Naitoh, Y.; et al. (2007). "New Nonvolatile Memory Effect Showing Reproducible Large Resistance Ratio Employing Nano-gap Gold Junction". MRS Symposium Proceedings 997: 0997–I04–08. doi:10.1557/PROC-0997-I04-08. 
  11. ^ Kayashima, S.; et al. (2007). "Control of Tunnel Resistance of Nanogaps by Field-Emission-Induced Electromigration". Jap. J. Appl. Phys. 46 (36–40): L907–909. doi:10.1143/JJAP.46.L907. 
  12. ^ Ahmed, Khaled; Schuegraf, Klaus (November 2011). "Transistor Wars: Rival architectures face off in a bid to keep Moore's Law alive". IEEE Spectrum: 50. 
  13. ^ Mehrotra, S.; et al. (2013). "Engineering Nanowire n-MOSFETs at Lg < 8 nm". Preprint. arXiv:1303.5458. 
  14. ^ Ballarotto, V. W.; et al. (2002). "Photoelectron emission microscopy of ultrathin oxide covered devices". JVST B 20 (6): 2514–2518. doi:10.1116/1.1525007. 
  15. ^ "Samsung Introduces Advanced Memory Storage Solution for Slim Smartphones and Tablets". 
  16. ^ "TSMC Launching 10 nm FinFET Process In 2016, 7nm In 2017". 19 April 2015. Retrieved 25 May 2015. 
  17. ^ "Samsung vows to start 10nm chip production in 2016". 23 May 2015. Retrieved 16 July 2015. 
  18. ^ "Samsung Mass Producing High-Performance 128-gigabit 3-bit Multi-level-cell NAND Flash Memory". Archived from the original on 2013-07-13. Retrieved 2013-07-10. 

Preceded by
14 nm
CMOS manufacturing processes Succeeded by
7 nm