256-bit computing

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In computer architecture, 256-bit integers, memory addresses, or other data units are those that are 256 bits (32 octets) wide. Also, 256-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers, address buses, or data buses of that size. There are currently no mainstream general-purpose processors built to operate on 256-bit integers or addresses, though a number of processors do operate on 256-bit data.

Representation[edit]

A 256-bit register can store 2256 different values. The range of integer values that can be stored in 256 bits depends on the integer representation used.

The maximum value of an unsigned 256-bit integer is 2256 − 1, written in decimal as 115,​792,​089,​237,​316,​195,​423,​570,​985,​008,​687,​907,​853,​269,​984,​665,​640,​564,​039,​457,​584,​007,​913,​129,​639,​935 or approximately as 1.1579 x 1077.

256-bit processors could be used for addressing directly up to 2256 bytes. Already 2128 (128-bit) would greatly exceed the total data stored on Earth as of 2010, which has been estimated to be around 1.2 zettabytes (over 270 bytes).[1]

Hardware[edit]

Laptop computer using an Efficeon processor

CPUs feature SIMD instruction sets (Advanced Vector Extensions and the FMA instruction set etc.) where 256-bit vector registers are used to store several smaller numbers, such as eight 32-bit floating-point numbers, and a single instruction can operate on all these values in parallel. However, these processors do not operate on individual numbers that are 256 binary digits in length, only their registers have the size of 256-bits. Binary digits are found together in 128-bit collections.

Modern GPU chips move data across a 256-bit memory bus (or possibly a 512-bit bus with HBM3[2]).

The Efficeon processor was Transmeta's second-generation 256-bit VLIW design which employed a software engine to convert code written for x86 processors to the native instruction set of the chip.[3][4]

The DARPA funded Data-Intensive Architecture (DIVA) system incorporated processor-in-memory (PIM) 5-stage pipelined 256-bit datapath, complete with register file and ALU blocks in a "WideWord" processor in 2002.[5]

Software[edit]

See also[edit]

References[edit]

  1. ^ Miller, Rich (4 May 2010). "Digital Universe nears a Zettabyte". Data Center Knowledge. Archived from the original on 6 May 2010. Retrieved 16 September 2010.
  2. ^ Harding, Scharon (15 April 2021). "What Are HBM, HBM2 and HBM2E? A Basic Definition". Tom's Hardware. Retrieved 2021-09-11.
  3. ^ "Transmeta Efficeon TM8300 Processor" (PDF). Transmeta Corporation. Archived (PDF) from the original on 10 February 2019.
  4. ^ Williams, Martyn (29 May 2002). "Transmeta Unveils Plans for TM8000 Processor". PC World. Archived from the original on 14 April 2010.
  5. ^ Draper, Jeffrey; Sondeen, Jeff; Chang Woo Kang (October 2002). Implementation of a 256-bit WideWord Processor for the Data-Intensive Architecture (DIVA) Processing-In-Memory (PIM) Chip (PDF). International Solid-State Circuits Conference. Archived (PDF) from the original on 29 August 2017.
  6. ^ Watson, Robert N. M.; Neumann, Peter G.; Woodruff, Jonathan; Anderson, Jonathan; Anderson, Ross; Dave, Nirav; Laurie, Ben; Moore, Simon W.; Murdoch, Steven J.; Paeps, Philip; Roe, Michael; Saidi, Hassen (3 March 2012). "CHERI: a research platform deconflating hardware virtualization and protection" (PDF). Unpublished workshop paper for RESoLVE’12, March 3, 2012, London, UK. SRI International Computer Science Laboratory.
  7. ^ Borisenkov, Dmitriy (23 October 2019). "[llvm-dev] RFC: On non 8-bit bytes and the target for it". Retrieved 2021-09-11.