32 nm process
The 32 nm node is the step following the 45 nm process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology level. Toshiba produced commercial 32 GiB NAND flash memory chips with the 32 nm process in 2009. Intel and AMD produced commercial microchips using the 32-nanometre process in the early 2010s. IBM and the Common Platform also developed a 32 nm high-κ metal gate process. Intel began selling its first 32 nm processors using the Westmere architecture on 7 January 2010.
The 28-nanometre node was an intermediate half-node die shrink based on the 32-nanometre process.
Prototypes using 32 nm technology first emerged in the mid-2000s, following the development of pitch double patterning by Gurtej Singh Sandhu at Micron Technology, which led to the development of NAND flash memory below 40 nm. In 2004, IBM demonstrated a 0.143 μm2 SRAM cell with a poly gate pitch of 135 nm, produced using electron-beam lithography and photolithography on the same layer. It was observed that the cell's sensitivity to input voltage fluctuations degraded significantly at such a small scale. In October 2006, the Interuniversity Microelectronics Centre (IMEC) demonstrated a 32 nm flash patterning capability based on double patterning and immersion lithography. The necessity of introducing double patterning and hyper-NA tools to reduce memory cell area offset some of the cost advantages of moving to this node from the 45 nm node. TSMC similarly used double patterning combined with immersion lithography to produce a 32 nm node 0.183 μm2 six-transistor SRAM cell in 2005.
Intel Corporation revealed its first 32 nm test chips to the public on 18 September 2007 at the Intel Developer Forum. The test chips had a cell size of 0.182 μm2, used a second-generation high-κ gate dielectric and metal gate, and contained almost two billion transistors. 193 nm immersion lithography was used for the critical layers, while 193 nm or 248 nm dry lithography was used on less critical layers. The critical pitch was 112.5 nm.
In January 2011, Samsung completed development of the industry's first DDR4 SDRAM module using a process technology with a size between 30 nm and 39 nm. The module could reportedly achieve data transfer rates of 2.133 Gbit/s at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent 30 nm-class process technology with speeds of up to 1.6 Gbit/s. The module used pseudo open drain (POD) technology, specially adapted to allow DDR4 SDRAM to consume just half the current of DDR3 when reading and writing data.
Processors using 32 nm technology
Intel's Core i3 and i5 processors, released in January 2010, were among the first mass-produced processors to use 32 nm technology. Intel's second-generation Core processors, codenamed Sandy Bridge, also used the 32 nm manufacturing process. Intel's 6-core processor, codenamed Gulftown and built on the Westmere architecture, was released on 16 March 2010 as the Core i7 980x Extreme Edition, retailing for approximately US$1,000. Intel's lower-end 6-core, the i7-970, was released in late July 2010, priced at approximately US$900.
AMD also released 32 nm SOI processors in the early 2010s. AMD's FX Series processors, codenamed Zambezi and based on AMD's Bulldozer architecture, were released in October 2011. The technology utilised a 32 nm SOI process, two CPU cores per module, and up to four modules, ranging from a quad-core design costing approximately US$130 to a $280 eight-core design.
The successor to 32 nm technology was the 22 nm node, per the International Technology Roadmap for Semiconductors. Intel began mass production of 22 nm semiconductors in late 2011, and announced the release of its first commercial 22 nm devices in April 2012. TSMC bypassed 32 nm, jumping from 40 nm in 2008 to 28 nm in 2011.
- "Toshiba Makes Major Advances in NAND Flash Memory with 3-bit-per-cell 32nm generation and with 4-bit-per-cell 43nm technology". Toshiba. 11 February 2009. Retrieved 21 June 2019.
- Intel (Architecture & Silicon). Gate Dielectric Scaling for CMOS: from SiO2/PolySi to High-K/Metal-Gate. White Paper. Intel.com. Retrieved 18 June 2013.
- "Report: Intel Scheduling 22 nm Ivy Bridge for April 2012". Tom'sHardware.com. 26 November 2011. Retrieved 5 December 2011.
- "Intel's Ivy Bridge chips launch using '3D transistors'". BBC. 23 April 2012. Retrieved 18 June 2013.
- "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Retrieved 4 July 2019.
- "Micron Named Among Top 100 Global Innovators for Sixth Straight Year". Micron Technology. 2018-02-15. Retrieved 5 July 2019.
- D. M. Fried et al., IEDM 2004.
- "IMEC demonstrates feasibility of double patterning immersion litho for 32nm node". PhysOrg.com. 18 October 2006. Retrieved 17 December 2011.
- Mark LaPedus (23 February 2007). "IBM sees immersion at 22nm, pushes out EUV". EE Times. Retrieved 11 November 2011.
- H-Y. Chen et al., Symp. on VLSI Tech. 2005.
- F. T. Chen (2002). Proc. SPIE. Vol. 4889, no. 1313.
- Peter Clarke (4 January 2011). "Samsung trials DDR4 DRAM module". EE Times. Retrieved 11 November 2011.
- "Intel Debuts 32-NM Westmere Desktop Processors". InformationWeek. 7 January 2010. Retrieved 17 December 2011.
- Sal Cangeloso (4 February 2010). "Intel's 6-core 32nm processors arriving soon". Geek.com. Retrieved 11 November 2011.
- "Ambarella A7L Enables the Next Generation of Digital Still Cameras with 1080p60 Fluid Motion Video". Ambarella.com. 26 September 2011. Archived from the original on 10 November 2011. Retrieved 11 November 2011.
- "Intel's CEO Discusses Q3 2011 Results - Earnings Call Transcript". Seeking Alpha. 18 October 2011. Retrieved 14 February 2013.
- "Intel beats analysts' first quarter forecasts". BBC. 17 April 2012. Retrieved 18 June 2013.
- "28nm Technology". TSMC. Retrieved 30 June 2019.
- Steen, S.; et al. (2006). "Hybrid lithography: The marriage between optical and e-beam lithography. A method to study process integration and device performance for advanced device nodes". Microelec. Eng. 83 (4–9): 754–761. doi:10.1016/j.mee.2006.01.181.
- Chipmakers gear up for manufacturing hurdles
- Sony, IBM, and Toshiba partnering on semiconductor research
- IBM and AMD partnering on semiconductor research
- Slashdot discussion
- Intel 32 nm process
- Samsung self-aligned double patterning technology
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