5 nanometer

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In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nanometer (5 nm) node as the technology node following the 7 nm node.



The 5 nm node was once assumed by some experts to be the end of Moore's law.[1] Transistors smaller than 7 nm will experience quantum tunnelling through the gate oxide layer.[2] Due to the costs involved in development, 5 nm is predicted to take longer to reach market than the two years estimated by Moore's law.[1]

Beyond 7 nm, it was initially claimed that major technological advances would have to be made to produce chips at this small scale.[citation needed] In particular, it is believed that 5 nm may usher in the successor to the FinFET, such as a gate-all-around architecture.

Technology demos[edit]

Single transistor 7 nm scale devices were first produced by researchers in the early 2000s.

In 2002, IBM produced a 6 nm transistor.[3]

In 2003, NEC produced a 5 nm transistor.[4]

In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.[5][6]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5 nm node.[7]

In 2017, IBM revealed that they had created 5 nm silicon chips,[8] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design.[9]


Although Intel has not yet revealed any specific plans to manufacturers or retailers, their 2009 roadmap projected an end-user release by approximately 2020.[10][11]

In early 2017, Samsung announced production of a 4 nm node by 2020 as part of its revised roadmap.[12]

On January 26th 2018, TSMC announced production of a 5 nm node by 2020 on its new fab 18.[13]

In October 2018, TSMC disclosed plans to start risk production of 5 nm devices in April 2019.[14]

5 nm process nodes[edit]

IRDS 2017




IRDS 2017


Process name 5nm 5nm 7nm
Transistor gate pitch (nm) 42 44 48
Interconnect pitch (nm) 24 32 28

Lower numbers are better. Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[16][17]

Beyond 5 nm[edit]

3.5 nm is a name for the first node beyond 5 nm.[18]

In 2018, IMEC and Cadence had taped out 3 nm test chips.[19] Also, Samsung announced that they plan to use Gate-All-Around technology to produce 3 nm FETs in 2021.[20]

Possible technologies that have been speculated to be useful or essential to producing chips beyond Moore's Law scaling have included: vortex laser,[21] MOSFET-BJT dual-mode transistor,[22] 3D packaging,[23] microfluidic cooling,[24] PCMOS,[25] vacuum transistors,[26] t-rays,[27] extreme ultraviolet lithography,[28] carbon nanotube transistors,[29] silicon photonics,[30] graphene,[31] phosphorene,[32] organic semiconductors,[33] gallium arsenide,[34] indium gallium arsenide,[35] nano-patterning,[36] and reconfigurable chaos-based microchips.[37]

Research and technology demos[edit]

In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center co-developed a 3 nm transistor, the world's smallest nanoelectronic device based on conventional finFET technology.[38][39] It was the smallest transistor ever produced at the time.

In 2008, transistors one atom thick and ten atoms wide were made by UK researchers. They were carved from graphene, a potential alternative to silicon as the basis of future computing. Graphene is a material made from flat sheets of carbon in a honeycomb arrangement, and is a leading contender. A team at the University of Manchester, UK, used it to make some of the smallest transistors at this time: devices only 1 nm across that contain just a few carbon rings.[40]

In 2010, an Australian team announced that they fabricated a single functional transistor out of 7 atoms that measured 4 nm in length.[41][42][43]

In 2012, a team of scientists at Chungbuk National University in South Korea created a 2 nm transistor.[44]

In 2012, a single-atom transistor was fabricated using a phosphorus atom bound to a silicon surface (between two significantly larger electrodes).[45] This transistor could be said to be a 360 picometer transistor, twice the van der Waals radius of a phosphorus atom; though its covalent radius bound to silicon is likely smaller.[46] Making transistors smaller than this will require either using elements with smaller atomic radii, or using subatomic particles—like electrons or protons—as functional transistors.

In 2016, researchers at Berkeley Lab created a transistor with a working 1 nm gate.[47][48] The field-effect transistor utilized MoS2 as the channel material, while a carbon nanotube was used to invert the channel. The effective channel length is approximately 1 nm. However, the drain to source pitch was much bigger, with micrometre size.

In 2018, researchers at Karlsruhe Institute of Technology created a transistor with a working single atom gate.[49]


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Preceded by
7 nm
CMOS manufacturing processes Succeeded by
3.5 nm (nanowire)