5 nm process
In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nm process as the MOSFET technology node following the 7 nm node. As of 2019, Samsung Electronics and TSMC have begun limited risk production of 5 nm nodes, and are planning to begin mass production in 2020.
The commercial 5 nm node is based on multi-gate MOSFET (MuGFET) technology, with FinFETs (fin field-effect transistors). 5 nm GAAFET (gate-all-around field-effect transistor) nodes had also been demonstrated, but not commercialized.
The 5 nm node was once assumed by some experts to be the end of Moore's law. Transistors smaller than 7 nm will experience quantum tunnelling through the gate oxide layer. Due to the costs involved in development, 5 nm is predicted to take longer to reach market than the two years estimated by Moore's law.
Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.
In 2017, IBM revealed that they had created 5 nm silicon chips, using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2.
In early 2018, TSMC expected to begin production of a 5 nm node by 2020 on its new Fab 18. In October 2018, TSMC announced plans to start testing or "risk production" of 5 nm devices by April 2019.
In April 2019, Samsung Electronics announced they had been offering their 5 nm process (5LPE) tools to their customers since 2018 Q4. In April 2019, TSMC announced that their 5 nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.
In October 2019, TSMC started sampling 5nm A14 processors for Apple.
In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their 5nm test chips with a die size of 17.92 mm2. The yield goes down to 32.0% with an increase in die size to 100 mm2. 
5 nm process nodes
|Samsung ||TSMC ||IRDS roadmap 2017|
|Process name (nm)||5LPE||N5||7||5|
|Transistor density (MTr/mm2)||127||173||222 (37×6)  †||300 (50×6)  †|
|SRAM bit-cell size (μm2)||0.026||0.017–0.019||0.027||0.020|
|Transistor gate pitch (nm)||57||48||48||42|
|Interconnect pitch (nm)||36||30||28||24|
|Risk production year||2018||2019||2019||2021|
|† Based on a 6T SRAM 111 cell|
Beyond 5 nm
3.5 nm has also been given as a name for the first node beyond 5 nm.
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Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).
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- Jones, Scotten, 7nm, 5nm and 3nm Logic, current and projected processes
- Schor, David (2019-04-06). "TSMC Starts 5-Nanometer Risk Production". WikiChip Fuse. Retrieved 2019-04-07.
- "IRDS international roadmap for devices and systems 2017 edition" (PDF).
- Jones, Scotten (May 3, 2019). "TSMC and Samsung 5nm Comparison". Semiwiki. Retrieved 30 July 2019.
- INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE (PDF), ITRS, 2017
- "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Semiconductors.org. Archived from the original (PDF) on 2 October 2016. Retrieved 7 December 2017.
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- "15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon". EETimes.com. 16 January 2017. Retrieved 4 June 2018.
7 nm (FinFET)
|MOSFET semiconductor device fabrication process||Succeeded by|
3 nm (GAAFET)