7 nm process
This article needs attention from an expert on the subject.May 2019)(
This article may be too technical for most readers to understand. Please help improve it to make it understandable to non-experts, without removing the technical details. (January 2020) (Learn how and when to remove this template message)
In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology.
Taiwan Semiconductor Manufacturing Company (TSMC) began production of 256 Mbit SRAM memory chips using a 7 nm process in 2017, before Samsung began mass production of 7 nm devices in 2018. The first mainstream 7 nm mobile processor intended for mass market use, the Apple A12 Bionic, was released at Apple's September 2018 event. Although Huawei announced its own 7 nm processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips are manufactured by TSMC.
AMD has released their "Rome"(Epyc 2) processors for servers and datacenters, which are based on TSMC's 7 nm node and feature up to 64 cores and 128 threads. They have also released their "Matisse" consumer desktop processors with 16 cores and 32 threads. However, the I/O die on the Rome multi-chip module (MCM) is fabricated with the 14 nm process, while the Matisse's I/O die uses the TSMC 12 nm process. The Radeon RX 5000 series is also based on the 7 nm process.
7 nm scale MOSFETs were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Turkish engineer Omer Dokumaci, Taiwanese engineer Meikei Ieong and Romanian engineer Anda Mocuta fabricated a 6 nm silicon-on-insulator (SOI) MOSFET. In 2003, NEC's research team led by Hitoshi Wakabayashi and Shigeharu Yamagami fabricated a 5 nm MOSFET.
Expected commercialization and technologies
In April 2016, TSMC announced that 7 nm trial production would begin in the first half of 2017. In April 2017, TSMC began risk production of 256 Mbit SRAM memory chips using a 7 nm (N7FF+) process, with extreme ultraviolet lithography (EUV). TSMC's 7 nm production plans, as of early 2017, were to use deep ultraviolet (DUV) immersion lithography initially on this process node (N7FF), and transition from risk to commercial volume manufacturing from Q2 2017 to Q2 2018. Also, their later generation 7 nm (N7FF+) production is planned to use EUV multiple patterning and to have an estimated transition from risk to volume manufacturing between 2018 and 2019.
In February 2017, Intel announced Fab 42 in Chandler, Arizona will produce microprocessors using 7 nm manufacturing process. The company has not published any expected values for feature lengths at this process node.
In April 2018, TSMC announced volume production of 7 nm (CLN7FF, N7) chips. In June 2018, the company announced mass production ramp up.
In August 2018, GlobalFoundries announced it was stopping development of 7 nm chips, citing cost.
On September 12, 2018, Apple announced their A12 Bionic chip used in iPhone XS and iPhone XR built using TSMC's 7 nm (N7) process. The A12 processor became the first 7 nm chip for mass market use as it released before the Huawei Mate 20. In October 30, 2018, Apple announced their A12X Bionic chip used in iPad Pro built using TSMC's 7 nm (N7) process.
On October 28, 2018, Samsung announced their second generation 7 nm process (7LPP) had entered risk production and should enter mass production in 2019.
On December 4, 2018, Qualcomm announced their Snapdragon 855 and 8cx built using TSMC's 7 nm (N7) process. The first mass product featuring the Snapdragon 855 was the Lenovo Z5 Pro GT, which was announced on December 18, 2018.
On January 17, 2019, for the Q4 2018 earnings call, TSMC mentioned that different customers will have "different flavors" of second generation 7 nm.
On April 16, 2019, TSMC announced their 6 nm process called (CLN6FF, N6), which is expected to be in mass products from 2021. N6 uses EUVL in up to 5 layers, compared to up to 4 layers in their N7+ process.
On July 28, 2019, TSMC announced their second gen 7 nm process called N7P, which is DUV-based like their N7 process. Since N7P is fully IP-compatible with the original 7 nm, while N7+ (which uses EUV) is not, N7+ (announced earlier as '7 nm+') is a separate process from '7 nm'. N6 ('6 nm'), another EUV-based process, is planned to be released later than even TSMC's 5 nm (N5) process, with the IP-compatibility with N7. At their Q1 2019 earnings call, TSMC reiterated their Q4 2018 statement that N7+ would generate less than $1 billion TWD in revenue in 2019.
On October 7, 2019, TSMC announced they started delivering N7+ products to market in high volume.
7 nm patterning difficulties
The 7 nm foundry node is expected to utilize any of or a combination of the following patterning technologies: pitch splitting, self-aligned patterning, and EUV lithography. Each of these technologies carries significant challenges in critical dimension (CD) control as well as pattern placement, all involving neighboring features.
Pitch splitting involves splitting features that are too close together onto different masks, which are exposed successively, followed by litho-etch processing. Due to the use of different exposures, there is always the risk of overlay error between the two exposures, as well as different CDs resulting from the different exposures.
Spacer patterning involves depositing a layer onto pre-patterned features, then etching back to form spacers on the sidewalls of those features, referred to as core features. After removing the core features, the spacers are used as an etch mask to define trenches in the underlying layer. While the spacer CD control is generally excellent, the trench CD may fall into one of two populations, due to the two possibilities of being located where a core feature was located or in the remaining gap. This is known as 'pitch walking'. Generally pitch = core CD + gap CD + 2 * spacer CD, but this does not guarantee core CD = gap CD. For FEOL features like gate or active area isolation (e.g., fins), the trench CD is not as critical as the spacer-defined CD, in which case, spacer patterning is actually the preferred patterning approach.
When self-aligned quadruple patterning (SAQP) is used, there is a second spacer that is utilized, replacing the first one. In this case, the core CD is replaced by core CD - 2* 2nd spacer CD, and the gap CD is replaced by gap CD - 2 * 2nd spacer CD. Thus, some feature dimensions are strictly defined by the second spacer CD, while the remaining feature dimensions are defined by the core CD, core pitch, and first and second spacer CD's. The core CD and core pitch are defined by conventional lithography, while the spacer CDs are independent of lithography. This is actually expected to have less variation than pitch splitting, where an additional exposure defines its own CD, both directly and through overlay.
Spacer-defined lines also require cutting. The cut spots may shift at exposure, resulting in distorted line ends or intrusions into adjacent lines.
Extreme ultraviolet lithography (also known as EUV or EUVL) is capable of resolving features below 20 nm in conventional lithography style. However, the 3D reflective nature of the EUV mask results in new anomalies in the imaging. One particular nuisance is the two-bar effect, where a pair of identical bar-shaped features do not focus identically. One feature is essentially in the 'shadow' of the other. Consequently, the two features generally have different CDs which change through focus, and these features also shift position through focus. This effect may be similar to what may be encountered with pitch splitting. A related issue is the difference of best focus among features of different pitches.
EUV also has issues with reliably printing all features in a large population; some contacts may be completely missing or lines bridged. These are known as stochastic printing failures. The defect level is on the order of 1K/mm2.
The tip-to-tip gap is hard to control for EUV, largely due to the illumination constraint. A separate exposure(s) for cutting lines is preferred.
Attenuated phase shift masks have been used in production for 90 nm node for adequate focus windows for arbitrarily pitched contacts with the ArF laser wavelength (193 nm), whereas this resolution enhancement is not available for EUV.
Comparison with previous nodes
Due to these challenges, 7 nm poses unprecedented patterning difficulty in the back end of line (BEOL). The previous high-volume, long-lived foundry node (Samsung 10 nm, TSMC 16 nm) used pitch splitting for the tighter pitch metal layers.
Cycle time: immersion vs. EUV
|Process||Immersion (≥ 275 WPH)||EUV (1500 wafers/day)|
1 day completion by immersion
|6000 wafers/day||1500 wafers/day|
2 days completion by immersion
|6000 wafers/2 days||3000 wafers/2 days|
3 days completion by immersion
|6000 wafers/3 days||4500 wafers/3 days|
4 days completion by immersion
|6000 wafers/4 days||6000 wafers/4 days|
Due to the immersion tools being faster presently, multipatterning is still used on most layers. On the layers requiring immersion quad-patterning, the layer completion throughput by EUV is comparable. On the other layers, immersion would be more productive at completing the layer even with multipatterning.
7 nm process nodes and process offerings
The naming of process nodes by different major manufacturers (TSMC, Intel, Samsung, GlobalFoundries) is partially marketing-driven and not directly related to any measurable distance on a chip – for example TSMC's 7 nm node is similar in some key dimensions to Intel's 10 nm node (see transistor density, gate pitch and metal pitch in the following table). Nevertheless, as of 2017, the technological race to the greatest density was still competitive between the main players, with TSMC, Samsung, and Intel all holding leading positions between the years 2016 and 2017 when measured by the smallest feature size on chip.
Since EUV implementation at 7 nm is still limited, multipatterning still plays an important part in cost and yield; EUV adds extra considerations. The resolution for most critical layers is still determined by multiple patterning. For example, for Samsung's 7 nm, even with EUV single-patterned 36 nm pitch layers, 44 nm pitch layers would still be quadruple patterned.
|TSMC N7FF||Samsung 7LPP||Intel 10 nm||TSMC N7P ('2nd generation 7 nm')||TSMC N7FF+||TSMC N6|
|Transistor density (MTr/mm2)||96.5||95.3 (7LPE)
|100.76||same as N7FF||113.9||114.2|
|SRAM bit-cell size||0.027 μm2||0.0262 μm2||0.0312 μm2||same as N7FF||Unknown||Unknown|
|Transistor Gate Pitch||54 nm||54 nm||54 nm||same as N7FF||Unknown||Unknown|
|Transistor Fin Pitch||Unknown||27 nm||34 nm||same as N7FF||Unknown||Unknown|
|Transistor Fin Height||Unknown||Unknown||53 nm||Unknown||Unknown||Unknown|
|Minimum (metal) pitch||40 nm||46 nm||36 nm||same as N7FF||< 40 nm||Unknown|
|EUV implementation||None, used self-aligned quad patterning (SAQP) instead||36 nm pitch metal;
20% of total layer set
|None. Relied on SAQP heavily||None||4 layers||5 layers|
|EUV-limited wafer output||N/A||1500 wafers/day||N/A||N/A||~ 1000 wafers/day||Unknown|
(≥ 2 masks on a layer)
Lowest 10 metal layers
Metal 1 (triple-patterned)
44 nm pitch metal (quad-patterned)
|Same as 7FF||Same as 7FF, with reduction on 4 EUV layers||Same as 7FF, with reduction on 5 EUV layers|
|Release status||2017 risk production
|2018 production||2018 limited production
planned, but no 2019 volume production
|2019 production||2018 risk production
7 nm design rule management in volume production
The 7 nm metal patterning currently practiced by TSMC involves self-aligned double patterning (SADP) lines with cuts inserted within a cell on a separate mask as needed to reduce cell height. However, self-aligned quad patterning (SAQP) is used to form the fin, the most important factor to performance. Design rule checks also allow via multi-patterning to be avoided, and provide enough clearances for cuts that only one cut mask is needed.
- "7nm Technology". TSMC. Retrieved June 30, 2019.
- TSMC ramping up 7nm chip production Monica Chen, Hsinchu; Jessie Shen, DIGITIMES Friday 22 June 2018
- "Apple's A12 Bionic CPU for the new iPhone XS is ahead of the industry moving to 7nm chip manufacturing tech". CNET. September 12, 2018. Retrieved September 16, 2018.
- "Apple's A12 Bionic is the first 7-nanometer smartphone chip". Engadget. Retrieved September 20, 2018.
- Smith, Ryan (July 26, 2018). "AMD "Rome" EPYC CPUs to Be Fabbed By TSMC". AnandTech. Retrieved June 18, 2019.
- "IBM claims world's smallest silicon transistor - TheINQUIRER". Theinquirer.net. December 9, 2002. Retrieved December 7, 2017.
- Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). "Extreme scaling with ultra-thin Si channel MOSFETs". Digest. International Electron Devices Meeting: 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2.
- "NEC test-produces world's smallest transistor". Thefreelibrary.com. Retrieved December 7, 2017.
- Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003: 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5.
- Dignan, Larry. "IBM Research builds functional 7nm processor". ZDNet.
- Markoff, John (July 9, 2015). "IBM Discloses Working Version of a Much Higher-Capacity Chip" – via NYTimes.com.
- "Beyond silicon: IBM unveils world's first 7nm chip – Ars Technica". arstechnica.com.
- "Seven Advancements for Beyond 7nm Chips". IBM Research Blog. February 27, 2017.
- Merritt, Rick (February 8, 2017), "TSMC, Samsung Diverge at 7nm", www.eetimes.com
- Parish, Kevin (April 20, 2016). "Watch out Intel and Samsung: TSMC is gearing up for 7 nm processing with trial production". www.digitaltrends.com.
- "TSMC Tips 7+, 12, 22nm Nodes | EE Times". EETimes. Retrieved March 17, 2017.
- Shilov, Anton (May 5, 2017), "Samsung and TSMC Roadmaps: 8 and 6 nm Added, Looking at 22ULP and 12FFC", www.anandtech.com, p. 2
- "GLOBALFOUNDRIES to Deliver Industry's Leading-Performance Offering of 7 nm FinFET Technology" (Press release). September 15, 2016. Retrieved April 8, 2017.
- "Intel Supports American Innovation with $7 Billion Investment in Next-Generation Semiconductor Factory in Arizona". Intel Newsroom.
- https://www.bloomberg.com/news/articles/2018-05-22/samsung-says-new-7-nanometer-chip-production-starting-this-year Samsung Says New 7-Nanometer Chip Production Starting This Year
- "Pushing Boundaries for CPUs and GPUs, AMD Shows Next-Generation of Ryzen, Radeon and EPYC Product Leadership at Computex 2018" (Press release). June 5, 2018.
- Martin, Dylan (August 23, 2018). "AMD CTO: 'We Went All In' On 7nm CPUs". CRN.
- https://www.engadget.com/2018/08/28/global-foundries-stops-7-nanometer-chip-production/ Major AMD chip supplier will no longer make next-gen chips
- "Apple Announces 'iPhone Xs' and 'iPhone Xs Max' With Gold Color, Faster Face ID, and More".
- "Apple Introduces 7nm A12 Bionic CPU for iPhone XS". Tom's Hardware. September 12, 2018. Retrieved September 12, 2018.
- "Apple walks Ars through the iPad Pro's A12X system on a chip". Ars Technica. Retrieved November 18, 2018.
- Cutress, Ian. "Qualcomm Tech Summit, Day 1: Announcing 5G Partnerships and Snapdragon 855". www.anandtech.com. Retrieved May 31, 2019.
- Frumusanu, Andrei. "Lenovo First to a Snapdragon 855 Phone with Announcement of Z5 Pro GT". www.anandtech.com. Retrieved May 31, 2019.
- Q4 2018 TSMC earnings call transcript, January 17, 2019.
- Schor, David (April 16, 2019). "TSMC Announces 6-Nanometer Process". WikiChip Fuse. Retrieved May 31, 2019.
- Shilov, Anton. "TSMC: Most 7nm Clients Will Transition to 6nm". www.anandtech.com. Retrieved May 31, 2019.
- Schor, David (July 28, 2019). "TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging". WikiChip Fuse. Retrieved September 13, 2019.
- C. C. Wei, TSMC Q1 2019 earnings call (April 18) transcript.
- MediaTek. "MediaTek 5G". i.mediatek.com. Retrieved May 31, 2019.
- "Samsung announces Exynos 9825 prior to Galaxy Note 10 launch". xda-developers. August 7, 2019. Retrieved September 13, 2019.
- Cutress, Dr Ian. "Huawei Announces Kirin 990 and Kirin 990 5G: Dual SoC Approach, Integrated 5G Modem". www.anandtech.com. Retrieved September 13, 2019.
- Frumusanu, Andrei. "Apple Announces New iPhone 11, iPhone 11 Pro, & iPhone 11 Pro Max". www.anandtech.com. Retrieved September 13, 2019.
- "AMD Dishes on Zen 3 and Zen 4 Architecture, Milan and Genoa Roadmap". Tom's Hardware. October 5, 2019. Retrieved October 8, 2019.
- "TSMC's N7+ Technology is First EUV Process Delivering Customer Products to Market in High Volume | Planet 3DNow!" (in German). Retrieved October 8, 2019.
- M. J. Maslow et al., Proc. SPIE 10587, 1058704 (2018).
- "IMEC EUVL 2018 Workshop" (PDF).
- Y. Nakajima et al., EUVL Symposium 2007, Sapporo.
- L. de Winter et al., Proc. SPIE 9661, 96610A (2015).
- M. Burkhardt and A. Raghunathan, Proc. SPIE 9422, 94220X (2015).
- P. De Bisschop and E. Hendrickx, Proc. SPIE 10583, 105831K (2018).
- "EUV's Stochastic Valley of Death". www.linkedin.com.
- S. Larivière et al., Proc. SPIE 10583, 105830U (2018).
- E. van Setten et al., Proc. SPIE 9661. 96610G (2015).
- C-H. Chang et al., Proc. SPIE 5377, 902 (2004).
- T. Devoivre et al., MTDT 2002.
- S-S. Yu et al., Proc. SPIE 8679, 86791L (2013).
- A. Erdmann et al., Proc. SPIE 10583, 1058312 (2018).
- Jeong, W. C.; Ahn, J. H.; Bang, Y. S.; Yoon, Y. S.; Choi, J. Y.; Kim, Y. C.; Paek, S. W.; Ahn, S. W.; Kim, B. S.; Song, T. J.; Jung, J. H.; Do, J. H.; Lim, S. M.; Cho, H.-; Lee, J. H.; Kim, D. W.; Kang, S. B.; Ku, J.-; Kwon, S. D.; Jung, S.-; Yoon, J. S. (June 23, 2017). "10nm 2nd generation BEOL technology with optimized illumination and LELELELE". 2017 Symposium on VLSI Technology. pp. T144–T145. doi:10.23919/VLSIT.2017.7998156. ISBN 978-4-86348-605-8 – via IEEE Xplore.
- "TSMC Symposium: "10nm is Ready for Design Starts at This Moment" - Industry Insights - Cadence Blogs - Cadence Community". community.cadence.com.
- Wu, S.; Lin, C. Y.; Chiang, M. C.; Liaw, J. J.; Cheng, J. Y.; Yang, S. H.; Liang, M.; Miyashita, T.; Tsai, C. H.; Hsu, B. C.; Chen, H. Y.; Yamamoto, T.; Chang, S. Y.; Chang, V. S.; Chang, C. H.; Chen, J. H.; Chen, H. F.; Ting, K. C.; Wu, Y. K.; Pan, K. H.; Tsui, R. F.; Yao, C. H.; Chang, P. R.; Lien, H. M.; Lee, T. L.; Lee, H. M.; Chang, W.; Chang, T.; Chen, R.; Yeh, M.; Chen, C. C.; Chiu, Y. H.; Chen, Y. H.; Huang, H. C.; Lu, Y. C.; Chang, C. W.; Tsai, M. H.; Liu, C. C.; Chen, K. S.; Kuo, C. C.; Lin, H. T.; Jang, S. M.; Ku, Y. (December 23, 2013). "A 16nm FinFET CMOS technology for mobile SoC and computing applications". 2013 IEEE International Electron Devices Meeting. pp. 9.1.1–9.1.4. doi:10.1109/IEDM.2013.6724591. ISBN 978-1-4799-2306-9 – via IEEE Xplore.
- "Products & services - Supplying the semiconductor industry". www.asml.com.
- "Samsung Ramps 7nm EUV Chips". EETimes. October 17, 2018.
- Merrit, Rick (January 16, 2017), "15 Views from a Silicon Summit", www.eetimes.com
- Hill, Brandon (March 28, 2017). "Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals". HotHardware.
- J. Kim et al., Proc. SPIE 10962, 1096204 (2019).
- IEDM 2016
- "VLSI 2018: Samsung's 2nd Gen 7nm, EUV Goes HVM". August 4, 2018.
- "Samsung Electronics Starts Production of EUV-based 7nm LPP Process". news.samsung.com.
- "TSMC Goes Photon to Cloud". EETimes. October 4, 2018.
- Jones, Scotten (May 3, 2019). "TSMC and Samsung 5nm Comparison". Semiwiki. Retrieved July 30, 2019.
- Nenni, Daniel (January 2, 2019). "Samsung vs TSMC 7nm Update". Semiwiki. Retrieved July 6, 2019.
- Schor, David (October 28, 2018). "Samsung 7nm Enters Risk Production, Talks Roadmap, Scaling Boosters, and the ARM Ecosystem". WikiChip Fuse. Retrieved May 31, 2019.
- Schor, David (June 15, 2018). "A Look at Intel's 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium". WikiChip Fuse. Retrieved May 31, 2019.
- "VLSI 2018: Samsung's 2nd Gen 7nm, EUV Goes HVM". WikiChip Fuse. August 4, 2018. Retrieved May 31, 2019.
- "TSMC Q1 2018 earnings call transcript, p.12" (PDF).
- Dillinger, Tom. "Top 10 Updates from the TSMC Technology Symposium, Part II".
- W. C. Jeong et al., VLSI Technology 2017.
- "A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology". Design And Reuse.
|MOSFET semiconductor device fabrication process||Succeeded by|