This article needs attention from an expert on the subject. The specific problem is: 7 nm Samsung/TSMC is equivalent to 10 nm Intel thus treating in different articles is marketing and not a real difference.May 2019)(
In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nanometer (7 nm) node as the technology node following the 10 nm node. Single transistor 7 nm scale devices were first produced in the early 2000s. While some claim that the node designation of "7 nm" has no physical meaning beyond marketing purposes, others point to transistor density as the real important number that is represented by these designations. The 7 nm process offerings by Samsung and TSMC are the same as the 10 nm process offered by Intel, thus, what really matters beyond 10 nm is transistor density (number of transistors per square milimeter), not transistor size. 
As of September 2018, mass production of 7 nm devices has begun. The first mainstream 7 nm mobile processor intended for mass market use, the Apple A12 Bionic, was released at their September 2018 event. Although Huawei announced its own 7 nm processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips are manufactured by TSMC. AMD is currently working on their "Rome" processors for servers and datacenters, which are based on the 7 nanometer node and feature up to 64 cores.
- 1 History
- 2 7 nm patterning difficulties
- 3 7 nm process nodes and process offerings
- 4 7 nm design rule management in volume production
- 5 References
Expected commercialization and technologies
In April 2016, TSMC announced that 7 nm trial production would begin in the first half of 2017. In March 2017, TSMC announced 7 nm with EUV (N7FF+) risk production starting by June 2018. TSMC's 7 nm production plans, as of early 2017, were to use DUV immersion lithography initially on this process node (N7FF), and transition from risk to commercial volume manufacturing from Q2 2017 to Q2 2018. Also, their later generation 7 nm (N7FF+) production is planned to use EUV multiple patterning and to have an estimated transition from risk to volume manufacturing between 2018 and 2019.
In February 2017, Intel announced Fab 42 in Chandler, Arizona will produce microprocessors using 7 nm manufacturing process. The company has not published any expected values for feature lengths at this process node.
In April 2018, TSMC announced volume production of 7 nm (CLN7FF, N7) chips. In June 2018, the company announced mass production ramp up.
In September 12, 2018, Apple announced their A12 Bionic chip used in iPhone XS and iPhone XR built using TSMC's 7 nm (N7) process. The A12 processor became the first 7 nm chip for mass market use as it released before the Huawei Mate 20. In October 30, 2018, Apple announced their A12X Bionic chip used in iPad Pro built using TSMC's 7 nm (N7) process.
In October 28, 2018, Samsung announced their second generation 7nm process (7LPP) had entered risk production and should enter mass production in 2019.
In December 4, 2018, Qualcomm announced their Snapdragon 855 and 8cx built using TSMC's 7 nm (N7) process. The first mass product featuring the Snapdragon 855 was the Lenovo Z5 Pro GT, which was announced on December 18, 2018.
In April 16, 2019, TSMC announced their 6 nm process called (CLN6FF, N6), which is expected to be in mass products from 2021. N6 uses EUVL in up to 5 layers, compared to up to 4 layers in their second gen 7nm process (CLN7FF+, N7+).
7 nm patterning difficulties
The 7 nm foundry node is expected to utilize any of or a combination of the following patterning technologies: pitch splitting, self-aligned patterning, and EUV lithography. Each of these technologies carries significant challenges in critical dimension (CD) control as well as pattern placement, all involving neighboring features.
Pitch splitting involves splitting features that are too close together onto different masks, which are exposed successively, followed by litho-etch processing. Due to the use of different exposures, there is always the risk of overlay error between the two exposures, as well as different CDs resulting from the different exposures.
Spacer patterning involves depositing a layer onto pre-patterned features, then etching back to form spacers on the sidewalls of those features, referred to as core features. After removing the core features, the spacers are used as an etch mask to define trenches in the underlying layer. While the spacer CD control is generally excellent, the trench CD may fall into one of two populations, due to the two possibilities of being located where a core feature was located or in the remaining gap. This is known as 'pitch walking'. Generally pitch = core CD + gap CD + 2 * spacer CD, but this does not guarantee core CD = gap CD. For FEOL features like gate or active area isolation (e.g., fins), the trench CD is not as critical as the spacer-defined CD, in which case, spacer patterning is actually the preferred patterning approach.
When self-aligned quadruple patterning (SAQP) is used, there is a second spacer that is utilized, replacing the first one. In this case, the core CD is replaced by core CD - 2* 2nd spacer CD, and the gap CD is replaced by gap CD - 2 * 2nd spacer CD. Thus, some feature dimensions are strictly defined by the second spacer CD, while the remaining feature dimensions are defined by the core CD, core pitch, and first and second spacer CD's. The core CD and core pitch are defined by conventional lithography, while the spacer CDs are independent of lithography. This is actually expected to have less variation than pitch splitting, where an additional exposure defines its own CD, both directly and through overlay.
Spacer-defined lines also require cutting. The cut spots may shift at exposure, resulting in distorted line ends or intrusions into adjacent lines.
Extreme ultraviolet lithography (also known as EUV or EUVL) is capable of resolving features below 20 nm in conventional lithography style. However, the 3D reflective nature of the EUV mask results in new anomalies in the imaging. One particular nuisance is the two-bar effect, where a pair of identical bar-shaped features do not focus identically. One feature is essentially in the 'shadow' of the other. Consequently, the two features generally have different CDs which change through focus, and these features also shift position through focus. This effect may be similar to what may be encountered with pitch splitting. A related issue is the difference of best focus among features of different pitches.
EUV also has issues with reliably printing all features in a large population; some contacts may be completely missing or lines bridged. These are known as stochastic printing failures. The defect level is on the order of 1K/mm2.
The tip-to-tip gap is hard to control for EUV, largely due to the illumination constraint. A separate exposure(s) for cutting lines is preferred.
Attenuated phase shift masks have been used in production for 90 nm node for adequate focus windows for arbitrarily pitched contacts with the ArF laser wavelength (193 nm), whereas this resolution enhancement is not available for EUV.
Comparison with previous nodes
Due to these challenges, 7 nm poses unprecedented patterning difficulty in the BEOL. The previous high-volume, long-lived foundry node (Samsung 10 nm, TSMC 16 nm) used pitch splitting for the tighter pitch metal layers.
Cycle time: immersion vs. EUV
|Process||Immersion (≥ 275 WPH)||EUV (1500 wafers/day)|
1 day completion by immersion
|6000 wafers/day||1500 wafers/day|
2 days completion by immersion
|6000 wafers/2 days||3000 wafers/2 days|
3 days completion by immersion
|6000 wafers/3 days||4500 wafers/3 days|
4 days completion by immersion
|6000 wafers/4 days||6000 wafers/4 days|
Due to the immersion tools being faster presently, multipatterning is still used on most layers. On the layers requiring immersion quad-patterning, the layer completion throughput by EUV is comparable. On the other layers, immersion would be more productive at completing the layer even with multipatterning.
7 nm process nodes and process offerings
The naming of process nodes by different major manufacturers (TSMC, Intel, Samsung, GlobalFoundries) is partially marketing-driven and not directly related to any measurable distance on a chip – for example TSMC's 7 nm node is similar in some key dimensions to Intel's 10 nm node. Nevertheless, as of 2017, the technological race to the greatest density was still competitive between the main players, with TSMC, Samsung, and Intel all holding leading positions between the years 2016 and 2017 when measured by the smallest feature size on chip.
Since EUV implementation at 7nm is still limited, multipatterning still plays an important part in cost and yield; EUV adds extra considerations. The resolution for most critical layers is still determined by multiple patterning. For example, for Samsung's 7nm, even with EUV single-patterned 36 nm pitch layers, 44 nm pitch layers would still be quadruple patterned.
|Intel 10 nm||TSMC N7FF||Samsung 7LPP||TSMC N7FF+||TSMC N6|
|Transistor density (MTr/mm2)||100.76||96.27||81.07 (57PP)
|SRAM bit-cell size||0.0312 µm²||0.027 µm²||0.0262 µm²||Unknown||Unknown|
|Transistor Gate Pitch||54 nm||54 nm||54 nm||Unknown||Unknown|
|Transistor Fin Pitch||34 nm||Unknown||27 nm||Unknown||Unknown|
|Transistor Fin Height||53 nm||Unknown||Unknown||Unknown||Unknown|
|Minimum (metal) pitch||36 nm||40 nm||46 nm||< 40 nm||Unknown|
|EUV implementation||None||None||36 nm pitch metal;
20% of total layer set
|4 layers||5 layers|
|EUV-limited wafer output||N/A||N/A||1500 wafers/day||~ 1000 wafers/day||Unknown|
(≥ 2 masks on a layer)
Lowest 10 metal layers
Metal 1 (triple-patterned)
44 nm pitch metal (quad-patterned)
|Same as 7FF, with reduction on 4 EUV layers||Same as 7FF, with reduction on 5 EUV layers|
|Release status||2018 / 2019 production||2018 production||2019 production||2019 production||2021 production|
7 nm design rule management in volume production
The 7nm metal patterning currently practiced by TSMC involves double patterning (LELE) lines with cuts inserted within a cell on a separate mask as needed to reduce cell height. Design rule checks also allow via multi-patterning to be avoided, and provide enough clearances for cuts that only one cut mask is needed.
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- Design Rule Check for 7nm ASIC Designs
|CMOS manufacturing processes||Succeeded by|
5 nm (gate-all-around)