7 nanometer

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In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nanometer (7 nm) node as the technology node following the 10 nm node. Single transistor 7 nm scale devices were first produced in the early 2000s. While some claim that the node designation of "7 nm" has no physical meaning beyond marketing purposes[citation needed], others point to transistor density as the real important number that is represented by these designations[citation needed]. The 7 nm process offerings by Samsung and TSMC are the same as the 10 nm process offered by Intel[citation needed], thus, what really matters beyond 10 nm is transistor density (number of transistors per square milimeter), not transistor size. [1]

As of September 2018, mass production of 7 nm devices has begun.[2] The first mainstream 7 nm mobile processor intended for mass market use, the Apple A12 Bionic, was released at their September 2018 event.[3] Although Huawei announced its own 7 nm processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips are manufactured by TSMC.[4] AMD is currently working on their "Rome" processors for servers and datacenters, which are based on the 7 nanometer node and feature up to 64 cores.

History[edit]

Technology demos[edit]

In July 2015, IBM announced that they had built the first functional transistors with 7 nm technology, using a silicon-germanium process.[5][6]

By early 2017, TSMC had produced 256 Mbit SRAM cells at their 7 nm process with a cell area of 0.027 mm2 (550 F2) with reasonable risk production yields.[7]

Expected commercialization and technologies[edit]

In April 2016, TSMC announced that 7 nm trial production would begin in the first half of 2017.[8] In March 2017, TSMC announced 7 nm with EUV (N7FF+) risk production starting by June 2018.[9] TSMC's 7 nm production plans, as of early 2017, were to use DUV immersion lithography initially on this process node (N7FF), and transition from risk to commercial volume manufacturing from Q2 2017 to Q2 2018. Also, their later generation 7 nm (N7FF+) production is planned to use EUV multiple patterning and to have an estimated transition from risk to volume manufacturing between 2018 and 2019.[10]

In September 2016, GlobalFoundries announced trial production in the second half of 2017 and risk production in early 2018, with test chips already running.[11]

In February 2017, Intel announced Fab 42 in Chandler, Arizona will produce microprocessors using 7 nm manufacturing process.[12] The company has not published any expected values for feature lengths at this process node.

In April 2018, TSMC announced volume production of 7 nm (CLN7FF, N7) chips. In June 2018, the company announced mass production ramp up.[2]

In May 2018, Samsung announced production of 7 nm chips this year. ASML Holding NV is their main supplier of EUV lithography machines.[13]

In June 2018, AMD announced 7 nm Radeon Instinct GPUs launching in the second half of 2018.[14] In August 2018, the company has confirmed the release of the GPUs.[15]

In August 2018, GlobalFoundries announced it was stopping development of 7 nm chips citing cost.[16]

In August 21, 2018, Huawei announced their HiSilicon Kirin 980 SoC to be used in their Huawei Mate 20 and Mate 20 Pro built using TSMC's 7 nm (N7) process.

In September 12, 2018, Apple announced their A12 Bionic chip used in iPhone XS and iPhone XR built using TSMC's 7 nm (N7) process. The A12 processor became the first 7 nm chip for mass market use as it released before the Huawei Mate 20.[17][18] In October 30, 2018, Apple announced their A12X Bionic chip used in iPad Pro built using TSMC's 7 nm (N7) process.[19]

In October 28, 2018, Samsung announced their second generation 7nm process (7LPP) had entered risk production and should enter mass production in 2019.

In December 4, 2018, Qualcomm announced their Snapdragon 855 and 8cx built using TSMC's 7 nm (N7) process.[20] The first mass product featuring the Snapdragon 855 was the Lenovo Z5 Pro GT, which was announced on December 18, 2018.[21]

In April 16, 2019, TSMC announced their 6 nm process called (CLN6FF, N6), which is expected to be in mass products from 2021.[22] N6 uses EUVL in up to 5 layers, compared to up to 4 layers in their second gen 7nm process (CLN7FF+, N7+).[23]

In May 29, 2019, MediaTek announced their 5G SoC built using a TSMC 7 nm process.[24]

7 nm patterning difficulties[edit]

Pitch splitting issues. Successive litho-etch patterning is subject to overlay errors as well as the CD errors from different exposures.
Spacer patterning issues. Spacer patterning has excellent CD control for features directly patterned by the spacer, but the spaces between spacers may be split into core and gap populations.
Overlay error impact on line cut. An overlay error on a cut hole exposure could distort the line ends (top) or infringe on an adjacent line (bottom).
Two-bar EUV patterning issues. In EUV lithography, a pair of features may not have both features in focus at the same time; one will have different size from the other, and both will shift differently through focus as well.
7nm EUV stochastic failure probability. 7nm features are expected to approach ~20 nm width. The probability of EUV stochastic failure is measurably high for the commonly applied dose of 30 mJ/cm2.

The 7 nm foundry node is expected to utilize any of or a combination of the following patterning technologies: pitch splitting, self-aligned patterning, and EUV lithography. Each of these technologies carries significant challenges in critical dimension (CD) control as well as pattern placement, all involving neighboring features.

Pitch splitting[edit]

Pitch splitting involves splitting features that are too close together onto different masks, which are exposed successively, followed by litho-etch processing. Due to the use of different exposures, there is always the risk of overlay error between the two exposures, as well as different CDs resulting from the different exposures.

Spacer patterning[edit]

Spacer patterning involves depositing a layer onto pre-patterned features, then etching back to form spacers on the sidewalls of those features, referred to as core features. After removing the core features, the spacers are used as an etch mask to define trenches in the underlying layer. While the spacer CD control is generally excellent, the trench CD may fall into one of two populations, due to the two possibilities of being located where a core feature was located or in the remaining gap. This is known as 'pitch walking'.[25] Generally pitch = core CD + gap CD + 2 * spacer CD, but this does not guarantee core CD = gap CD. For FEOL features like gate or active area isolation (e.g., fins), the trench CD is not as critical as the spacer-defined CD, in which case, spacer patterning is actually the preferred patterning approach.

When self-aligned quadruple patterning (SAQP) is used, there is a second spacer that is utilized, replacing the first one. In this case, the core CD is replaced by core CD - 2* 2nd spacer CD, and the gap CD is replaced by gap CD - 2 * 2nd spacer CD. Thus, some feature dimensions are strictly defined by the second spacer CD, while the remaining feature dimensions are defined by the core CD, core pitch, and first and second spacer CD's. The core CD and core pitch are defined by conventional lithography, while the spacer CDs are independent of lithography. This is actually expected to have less variation than pitch splitting, where an additional exposure defines its own CD, both directly and through overlay.

Spacer-defined lines also require cutting. The cut spots may shift at exposure, resulting in distorted line ends or intrusions into adjacent lines.

EUV lithography[edit]

Extreme ultraviolet lithography (also known as EUV or EUVL) is capable of resolving features below 20 nm in conventional lithography style. However, the 3D reflective nature of the EUV mask results in new anomalies in the imaging. One particular nuisance is the two-bar effect, where a pair of identical bar-shaped features do not focus identically. One feature is essentially in the 'shadow' of the other. Consequently, the two features generally have different CDs which change through focus, and these features also shift position through focus.[26][27][28] This effect may be similar to what may be encountered with pitch splitting. A related issue is the difference of best focus among features of different pitches.[29]

EUV also has issues with reliably printing all features in a large population; some contacts may be completely missing or lines bridged. These are known as stochastic printing failures.[30][31] The defect level is on the order of 1K/mm2.[32]

The tip-to-tip gap is hard to control for EUV, largely due to the illumination constraint.[33] A separate exposure(s) for cutting lines is preferred.

Attenuated phase shift masks have been used in production for 90 nm node for adequate focus windows for arbitrarily pitched contacts with the ArF laser wavelength (193 nm),[34][35] whereas this resolution enhancement is not available for EUV.[36][37]

Comparison with previous nodes[edit]

Due to these challenges, 7 nm poses unprecedented patterning difficulty in the BEOL. The previous high-volume, long-lived foundry node (Samsung 10 nm, TSMC 16 nm) used pitch splitting for the tighter pitch metal layers.[38][39][40]

Cycle time: immersion vs. EUV[edit]

Process Immersion (≥ 275 WPH)[41] EUV (1500 wafers/day)[42]
Single-patterned layer:
1 day completion by immersion
6000 wafers/day 1500 wafers/day
Double-patterned layer:
2 days completion by immersion
6000 wafers/2 days 3000 wafers/2 days
Triple-patterned layer:
3 days completion by immersion
6000 wafers/3 days 4500 wafers/3 days
Quad-patterned layer:
4 days completion by immersion
6000 wafers/4 days 6000 wafers/4 days

Due to the immersion tools being faster presently, multipatterning is still used on most layers. On the layers requiring immersion quad-patterning, the layer completion throughput by EUV is comparable. On the other layers, immersion would be more productive at completing the layer even with multipatterning.

7 nm process nodes and process offerings[edit]

The naming of process nodes by different major manufacturers (TSMC, Intel, Samsung, GlobalFoundries) is partially marketing-driven and not directly related to any measurable distance on a chip – for example TSMC's 7 nm node is similar in some key dimensions to Intel's 10 nm node. Nevertheless, as of 2017, the technological race to the greatest density was still competitive between the main players, with TSMC, Samsung, and Intel all holding leading positions between the years 2016 and 2017 when measured by the smallest feature size on chip.[43][44]

Since EUV implementation at 7nm is still limited, multipatterning still plays an important part in cost and yield; EUV adds extra considerations. The resolution for most critical layers is still determined by multiple patterning. For example, for Samsung's 7nm, even with EUV single-patterned 36 nm pitch layers, 44 nm pitch layers would still be quadruple patterned.[45]

Intel 10 nm TSMC N7FF[46] Samsung 7LPP[47][48] TSMC N7FF+[49] TSMC N6
Transistor density (MTr/mm2) 100.76[50] 96.27[22] 81.07 (57PP)

85.57 (54PP)[51]

Unknown 114.2[22]
SRAM bit-cell size 0.0312 µm² 0.027 µm²[52] 0.0262 µm²[52] Unknown Unknown
Transistor Gate Pitch 54 nm 54 nm 54 nm Unknown Unknown
Transistor Fin Pitch 34 nm Unknown 27 nm Unknown Unknown
Transistor Fin Height 53 nm Unknown Unknown Unknown Unknown
Minimum (metal) pitch 36 nm 40 nm 46 nm < 40 nm Unknown
EUV implementation None None 36 nm pitch metal;[45]
20% of total layer set
4 layers 5 layers
EUV-limited wafer output N/A N/A 1500 wafers/day[42] ~ 1000 wafers/day[53] Unknown
Multipatterning
(≥ 2 masks on a layer)
Fins
Gate
Contacts/vias (quad-patterned)[54]
Lowest 10 metal layers
Fins
Gate
Vias (double-patterned)[55]
Metal 1 (triple-patterned)[55]
44 nm pitch metal (quad-patterned)[45]
Same as 7FF, with reduction on 4 EUV layers Same as 7FF, with reduction on 5 EUV layers
Release status 2018 / 2019 production 2018 production 2019 production 2019 production 2021 production

7 nm design rule management in volume production[edit]

The 7nm metal patterning currently practiced by TSMC involves double patterning (LELE) lines with cuts inserted within a cell on a separate mask as needed to reduce cell height.[56] Design rule checks also allow via multi-patterning to be avoided, and provide enough clearances for cuts that only one cut mask is needed.[56]

References[edit]

  1. ^ "The iPhone XS & XS Max Review: Unveiling the Silicon Secrets (Page 2:The Apple A12 - First Commercial 7nm Silicon)". AnandTech. 5 Oct 2018. Retrieved 6 Oct 2018.
  2. ^ a b TSMC ramping up 7nm chip production Monica Chen, Hsinchu; Jessie Shen, DIGITIMES Friday 22 June 2018
  3. ^ "Apple's A12 Bionic CPU for the new iPhone XS is ahead of the industry moving to 7nm chip manufacturing tech". CNET. 2018-09-12. Retrieved 2018-09-16.
  4. ^ "Apple's A12 Bionic is the first 7-nanometer smartphone chip". Engadget. Retrieved 2018-09-20.
  5. ^ IBM Research builds functional 7nm processor
  6. ^ IBM Discloses Working Version of a Much Higher-Capacity Chip - NYTimes.com
  7. ^ Merritt, Rick (8 Feb 2017), "TSMC, Samsung Diverge at 7nm", www.eetimes.com
  8. ^ Parish, Kevin (20 Apr 2016). "Watch out Intel and Samsung: TSMC is gearing up for 7 nm processing with trial production". www.digitaltrends.com.
  9. ^ "TSMC Tips 7+, 12, 22nm Nodes | EE Times". EETimes. Retrieved 2017-03-17.
  10. ^ Shilov, Anton (5 May 2017), "Samsung and TSMC Roadmaps: 8 and 6 nm Added, Looking at 22ULP and 12FFC", www.anandtech.com, p. 2
  11. ^ "GLOBALFOUNDRIES to Deliver Industry's Leading-Performance Offering of 7 nm FinFET Technology" (Press release). September 15, 2016. Retrieved April 8, 2017.
  12. ^ Intel Supports American Innovation with $7 Billion Investment in Next-Generation Semiconductor Factory in Arizona: Intel’s Fab 42 will Target Advanced 7 nm Technology and Create More Than 10,000 Jobs in Arizona
  13. ^ https://www.bloomberg.com/news/articles/2018-05-22/samsung-says-new-7-nanometer-chip-production-starting-this-year Samsung Says New 7-Nanometer Chip Production Starting This Year
  14. ^ "Pushing Boundaries for CPUs and GPUs, AMD Shows Next-Generation of Ryzen, Radeon and EPYC Product Leadership at Computex 2018" (Press release). June 5, 2018.
  15. ^ https://www.crn.com/news/components-peripherals/amd-cto-we-went-all-in-on-7nm-cpus
  16. ^ https://www.engadget.com/2018/08/28/global-foundries-stops-7-nanometer-chip-production/ Major AMD chip supplier will no longer make next-gen chips
  17. ^ "Apple Announces 'iPhone Xs' and 'iPhone Xs Max' With Gold Color, Faster Face ID, and More".
  18. ^ "Apple Introduces 7nm A12 Bionic CPU for iPhone XS". Tom's Hardware. 2018-09-12. Retrieved 2018-09-12.
  19. ^ "Apple walks Ars through the iPad Pro's A12X system on a chip". Ars Technica. Retrieved 2018-11-18.
  20. ^ Cutress, Ian. "Qualcomm Tech Summit, Day 1: Announcing 5G Partnerships and Snapdragon 855". www.anandtech.com. Retrieved 2019-05-31.
  21. ^ Frumusanu, Andrei. "Lenovo First to a Snapdragon 855 Phone with Announcement of Z5 Pro GT". www.anandtech.com. Retrieved 2019-05-31.
  22. ^ a b c Schor, David (2019-04-16). "TSMC Announces 6-Nanometer Process". WikiChip Fuse. Retrieved 2019-05-31.
  23. ^ Shilov, Anton. "TSMC: Most 7nm Clients Will Transition to 6nm". www.anandtech.com. Retrieved 2019-05-31.
  24. ^ MediaTek. "MediaTek 5G". i.mediatek.com. Retrieved 2019-05-31.
  25. ^ M. J. Maslow et al., Proc. SPIE 10587, 1058704 (2018).
  26. ^ IMEC EUVL 2018 Workshop
  27. ^ Y. Nakajima et al., EUVL Symposium 2007, Sapporo.
  28. ^ L. de Winter et al., Proc. SPIE 9661, 96610A (2015).
  29. ^ M. Burkhardt and A. Raghunathan, Proc. SPIE 9422, 94220X (2015).
  30. ^ P. De Bisschop and E. Hendrickx, Proc. SPIE 10583, 105831K (2018).
  31. ^ EUV's Stochastic Valley of Death
  32. ^ S. Larivière et al., Proc. SPIE 10583, 105830U (2018).
  33. ^ E. van Setten et al., Proc. SPIE 9661. 96610G (2015).
  34. ^ C-H. Chang et al., Proc. SPIE 5377, 902 (2004).
  35. ^ T. Devoivre et al., MTDT 2002.
  36. ^ S-S. Yu et al., Proc. SPIE 8679, 86791L (2013).
  37. ^ A. Erdmann et al., Proc. SPIE 10583, 1058312 (2018).
  38. ^ Samsung's 2nd generation 10nm by LELELELE
  39. ^ tsmc 10nm starts
  40. ^ 16nm FinFET CMOS
  41. ^ NXT:1980Di spec
  42. ^ a b Samsung 7nm EUV
  43. ^ Merrit, Rick (16 Jan 2017), "15 Views from a Silicon Summit", www.eetimes.com
  44. ^ "Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals".
  45. ^ a b c J. Kim et al., Proc. SPIE 10962, 1096204 (2019).
  46. ^ IEDM 2016
  47. ^ VLSI 2018
  48. ^ Samsung starts 7LPP
  49. ^ EETimes 1333827
  50. ^ Schor, David (2018-06-15). "A Look at Intel's 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium". WikiChip Fuse. Retrieved 2019-05-31.
  51. ^ Schor, David (2018-10-28). "Samsung 7nm Enters Risk Production, Talks Roadmap, Scaling Boosters, and the ARM Ecosystem". WikiChip Fuse. Retrieved 2019-05-31.
  52. ^ a b "VLSI 2018: Samsung's 2nd Gen 7nm, EUV Goes HVM". WikiChip Fuse. 2018-08-04. Retrieved 2019-05-31.
  53. ^ TSMC Q1 2018 earnings call transcript, p.12
  54. ^ TSMC Technology Symposium 2017
  55. ^ a b W. C. Jeong et al., VLSI Technology 2017.
  56. ^ a b Design Rule Check for 7nm ASIC Designs


Preceded by
10 nm
CMOS manufacturing processes Succeeded by
5 nm (gate-all-around)