Flat memory model
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Flat memory model or linear memory model refers to a memory addressing paradigm in which "memory appears to the program as a single contiguous address space."[1] The CPU can directly (and linearly) address all of the available memory locations without having to resort to any sort of bank switching, memory segmentation or paging schemes.
Memory management and address translation can still be implemented on top of a flat memory model in order to facilitate the operating system's functionality, resource protection, multitasking or to increase the memory capacity beyond the limits imposed by the processor's physical address space, but the key feature of a flat memory model is that the entire memory space is linear, sequential and contiguous.
In a simple controller, or in a single tasking embedded application, where memory management is not needed nor desirable, the flat memory model is the most appropriate, because it provides the simplest interface from the programmer's point of view, with direct access to all memory locations and minimum design complexity.
In a general purpose computer system, which requires multitasking, resource allocation, and protection, the flat memory system must be augmented by some memory management scheme, which is typically implemented through a combination of dedicated hardware (inside or outside the CPU) and software built into the operating system. The flat memory model (at the physical addressing level) still provides the greatest flexibility for implementing this type of memory management.
Memory models
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Most modern memory models fall into one of three categories:
Flat memory model
- Simple interface for programmers, clean design
- Greatest flexibility due to uniform access speed (segmented memory page switches usually incur varied latency due to longer accesses of other pages, either due to extra CPU logic in changing page, or hardware requirements)
- Minimum hardware and CPU real estate for simple controller applications[clarification needed]
- Maximum execution speed, Simply there isn't any latency due to CPU or logic.[why?]
- Not suitable for general computing or multitasking operating systems unless enhanced[why?] with additional memory management hardware/software; but this is almost always the case in modern CISC processors, which implement advanced memory management and protection technology over a flat memory model. Linux e.g. uses a flat memory model, see x86 memory segmentation#Practices.
Paged memory model
- Suitable for multitasking, general operating system design, resource protection and allocation
- Suitable for virtual memory implementation
- More CPU real estate, somewhat lower speed
- More complex to program
- Rigid page boundaries, not always the most memory efficient
- This memory model is required when using Physical Address Extension (PAE) in Pentium Pro and later x86 CPUs to support 36-bit physical addresses to address more than 4GB of physical memory.
x86 segmented memory model
- Similar to paged memory, but paging is achieved by the implicit addition of two relatively shifted registers: segment:offset
- Variable page boundaries, more efficient and flexible than the paged memory model
- Quite complex and awkward from a programmer's point of view
- More difficult for compilers
- Pages can overlap / poor resource protection and isolation
- Many to one address translation correspondence: Many segment:offset combinations resolve to the same physical address
- Greater chance of programming errors
- Implemented in the original Intel 8086, 8088, 80186, 80286, and supported by 80386 and all subsequent x86 machines through to present day Pentium and Core 2 processors. This memory model has remained ever since in the x86 machines, which now provide multi-mode operation and rarely operate in the compatible segmented mode.[clarification needed] See x86 memory segmentation for details.
- saves RAM by moving the segment address, this allows short jumps that require fewer bytes.
Within the x86 architectures, when operating in the real mode (or emulation), physical address is computed as:[2]
- Address = 16 × segment + offset
(I.e., the 16-bit segment register is shifted left by 4 bits and added to a 16-bit offset, resulting in a 20-bit address.)
See also
References
- ^ Gonzalez, Antonio; Latorre, Fernando; Magklis, Grigorios (2011). Processor Microarchitecture: An Implementation Perspective. Morgan & Claypool Publishers. p. 72. ISBN 9781608454525.
- ^ General description of Real Mode "The physical address can be calculated as Value_in_segment_register
- 16 + Value_in_offset_register."