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AArch64 or ARM64 is the 64-bit extension of the ARM architecture.

ARMv8-A Platform with Cortex A57/A53 MPCore big.LITTLE CPU chip

It was first introduced with the ARMv8-A architecture.


Announced in October 2011,[1] ARMv8-A (often called just ARMv8, although there is also a 32-bit ARMv8-R) represents a fundamental change to the ARM architecture. It adds an optional 64-bit architecture (e.g. Cortex-A32 is a 32-bit ARMv8-A CPU[2] while most ARMv8-A CPUs support 64-bit, unlike all ARMv8-R), named "AArch64", and the associated new "A64" instruction set. AArch64 provides user-space compatibility with ARMv7-A, the 32-bit architecture, therein referred to as "AArch32" and the old 32-bit instruction set, now named "A32". The Thumb instruction set is referred to as "T32" and has no 64-bit counterpart. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor.[3] ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.[4] Apple was the first to release an ARMv8-A compatible core (Apple A7) in a consumer product (iPhone 5S). AppliedMicro, using an FPGA, was the first to demo ARMv8-A.[5] The first ARMv8-A SoC from Samsung is the Exynos 5433 used in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it will run only in AArch32 mode.[6]

To both AArch32 and AArch64, ARMv8-A makes VFPv3/v4 and advanced SIMD (Neon) standard. It also adds cryptography instructions supporting AES, SHA-1/SHA-256 and finite field arithmetic.[7]

AArch64 features[edit]

  • New instruction set, A64
    • Has 31 general-purpose 64-bit registers.
    • Has dedicated zero or stack pointer (SP) register (depending on instruction).
    • The program counter (PC) is no longer directly accessible as a register.
    • Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped).
      • Has paired loads/stores (in place of LDM/STM).
      • No predication for most instructions (except branches).
    • Most instructions can take 32-bit or 64-bit arguments.
    • Addresses assumed to be 64-bit.
  • Advanced SIMD (Neon) enhanced
  • A new exception system
    • Fewer banked registers and modes.
  • Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension (LPAE), which was designed to be easily extended to 64-bit.

AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMV8-A. AArch64 is not included in ARMv8-R or ARMv8-M, because they are both 32-bit architectures.


In December 2014, ARMv8.1-A,[8] an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation.

Instruction set enhancements included the following:

  • A set of AArch64 atomic read-write instructions.
  • Additions to the Advanced SIMD instruction set for both AArch32 and AArch64 to enable opportunities for some library optimizations:
    • Signed Saturating Rounding Doubling Multiply Accumulate, Returning High Half.
    • Signed Saturating Rounding Doubling Multiply Subtract, Returning High Half.
    • The instructions are added in vector and scalar forms.
  • A set of AArch64 load and store instructions that can provide memory access order that is limited to configurable address regions.
  • The optional CRC instructions in v8.0 become a requirement in ARMv8.1.

Enhancements for the exception model and memory translation system included the following:

  • A new Privileged Access Never (PAN) state bit provides control that prevents privileged access to user data unless explicitly enabled.
  • An increased VMID range for virtualization; supports a larger number of virtual machines.
  • Optional support for hardware update of the page table access flag, and the standardization of an optional, hardware updated, dirty bit mechanism.
  • The Virtualization Host Extensions (VHE). These enhancements improve the performance of Type 2 hypervisors by reducing the software overhead associated when transitioning between the Host and Guest operating systems. The extensions allow the Host OS to execute at EL2, as opposed to EL1, without substantial modification.
  • A mechanism to free up some translation table bits for operating system use, where the hardware support is not needed by the OS.
  • Top byte ignore for memory tagging.[9]


In January 2016, ARMv8.2-A was announced.[10] Its enhancements fell into four categories:

Scalable Vector Extension (SVE) [edit]

The Scalable Vector Extension (SVE) is "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization of high-performance computing scientific workloads.[11][12] The specification allows for variable vector lengths to be implemented from 128 to 2048 bits. The extension is completementary to, and does not replace, the NEON extensions.

A 512-bit SVE variant has already been implemented on the Fugaku supercomputer using the Fujitsu A64FX ARM processor. It aims to be the world's highest-performing supercomputer with "the goal of beginning full operations around 2021."[13]

SVE is supported by the GCC compiler, with GCC 8 supporting automatic vectorization[12] and GCC 10 supporting C intrinsics. As of July 2020, LLVM and clang support C and IR intrinsics. ARM's own fork of LLVM supports auto-vectorization.[14]


In October 2016, ARMv8.3-A was announced. Its enhancements fell into six categories:[15]

  • Pointer authentication[16] (AArch64 only); mandatory extension (based on a new block cipher, QARMA[17]) to the architecture (compilers need to exploit the security feature, but as the instructions are in NOP space, they are backwards compatible albeit providing no extra security on older chips).
  • Nested virtualization (AArch64 only)
  • Advanced SIMD complex number support (AArch64 and AArch32); e.g. rotations by multiples of 90 degrees.
  • New FJCVTZS (Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero) instruction.[18]
  • A change to the memory consistency model (AArch64 only); to support the (non-default) weaker RCpc (Release Consistent processor consistent) model of C++11/C11 (the default C++11/C11 consistency model was already supported in previous ARMv8).
  • ID mechanism support for larger system-visible caches (AArch64 and AArch32)

ARMv8.3-A architecture is now supported by (at least) the GCC 7 compiler.[19]


In November 2017, ARMv8.4-A was announced. Its enhancements fell into these categories:[20][21][22]

  • "SHA3 / SHA512 / SM3 / SM4 crypto extensions"
  • Improved virtualization support
  • Memory Partitioning and Monitoring (MPAM) capabilities
  • A new Secure EL2 state and Activity Monitors
  • Signed and unsigned integer dot product (SDOT and UDOT) instructions.


In September 2018 ARMv8.5-A was announced. Its enhancements fell into these categories:[23][24]

  • Memory Tagging Extension (MTE),
  • Branch Target Indicators (BTI) to reduce "the ability of an attacker to execute arbitrary code"
  • Random Number Generator instructions – "providing Deterministic and True Random Numbers conforming to various National and International Standards."

On 2 August 2019, Google announced Android would adopt Memory Tagging Extension (MTE).[25]


In September 2019, ARMv8.6-A was announced. It adds:[26]

  • General Matrix Multiply (GEMM)
  • Bfloat16 format support
  • SIMD matrix manipulation instructions, BFDOT, BFMMLA, BFMLAL and BFCVT
  • enhancements for virtualization, system management and security

For example, Fine grained traps, Wait-for-Event (WFE) instructions, EnhancedPAC2 and FPAC. The Bfloat16 extensions for SVE and Neon are mainly for deep learning use.[27]

Future ARM architecture features[edit]

In May 2019, ARM announced their upcoming Scalable Vector Extension 2 (SVE2) and Transactional Memory Extension (TME).[28]

Scalable Vector Extension 2 (SVE2)[edit]

SVE2 builds on SVE's scalable vectorization for increased fine-grain Data Level Parallelism (DLP), to allow more work done per instruction. SVE2 aims to bring these benefits to a wider range of software including DSP and multimedia SIMD code that currently use Neon.[28] The LLVM/Clang 9.0 and GCC 10.0 development codes were updated to support SVE2.[29]

Transactional Memory Extension (TME)[edit]

Following the x86 extensions, TME brings support for Hardware Transactional Memory (HTM) and Transactional Lock Elision (TLE). TME aims to bring scalable concurrency to increase coarse-grained Thread Level Parallelism (TLP), to allow more work done per thread.[28] The LLVM/Clang 9.0 and GCC 10.0 development codes were updated to support TME.[29]


  1. ^ "ARM Discloses Technical Details Of The Next Version Of The ARM Architecture" (Press release). Arm Holdings. 27 October 2011. Archived from the original on 1 January 2019. Retrieved 20 September 2013.
  2. ^ "Cortex-A32 Processor – ARM". Retrieved 18 December 2016.
  3. ^ Grisenthwaite, Richard (2011). "ARMv8-A Technology Preview" (PDF). Retrieved 31 October 2011.
  4. ^ "ARM Launches Cortex-A50 Series, the World's Most Energy-Efficient 64-bit Processors" (Press release). Arm Holdings. Retrieved 31 October 2012.
  5. ^ "AppliedMicro Showcases World's First 64-bit ARM v8 Core" (Press release). AppliedMicro. 28 October 2011. Retrieved 11 February 2014.
  6. ^ "Samsung's Exynos 5433 is an A57/A53 ARM SoC". AnandTech. Retrieved 17 September 2014.
  7. ^ "ARM Cortex-A53 MPCore Processor Technical Reference Manual: Cryptography Extension". ARM. Retrieved 11 September 2016.
  8. ^ Brash, David (2 December 2014). "The ARMv8-A architecture and its ongoing development". Retrieved 23 January 2015.
  9. ^ "TBI".
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  11. ^ "The scalable vector extension sve for the Armv8 a architecture". Arm Community. 22 August 2016. Retrieved 8 July 2018.
  12. ^ a b "GCC 8 Release Series – Changes, New Features, and Fixes – GNU Project – Free Software Foundation (FSF)". gcc.gnu.org. Retrieved 9 July 2018.
  13. ^ "Fujitsu Completes Post-K Supercomputer CPU Prototype, Begins Functionality Trials – Fujitsu Global". www.fujitsu.com (Press release). Retrieved 8 July 2018.
  14. ^ "⚙ D71712 Downstream SVE/SVE2 implementation (LLVM)". reviews.llvm.org.
  15. ^ David Brash (26 October 2016). "ARMv8-A architecture – 2016 additions".
  16. ^ "[Ping~,AArch64] Add commandline support for -march=armv8.3-a". pointer authentication extension is defined to be mandatory extension on ARMv8.3-A and is not optional
  17. ^ "Qualcomm releases whitepaper detailing pointer authentication on ARMv8.3".
  18. ^ "A64 Floating-point Instructions: FJCVTZS". arm.com. Retrieved 11 July 2019.
  19. ^ "GCC 7 Release Series – Changes, New Features, and Fixes". The ARMv8.3-A architecture is now supported. It can be used by specifying the -march=armv8.3-a option. [..] The option -msign-return-address= is supported to enable return address protection using ARMv8.3-A Pointer Authentication Extensions.
  20. ^ "Introducing 2017's extensions to the Arm Architecture". community.arm.com. Retrieved 15 June 2019.
  21. ^ "Exploring dot product machine learning". community.arm.com. Retrieved 15 June 2019.
  22. ^ "ARM Preps ARMv8.4-A Support For GCC Compiler – Phoronix". www.phoronix.com. Retrieved 14 January 2018.
  23. ^ "Arm Architecture Armv8.5-A Announcement – Processors blog – Processors – Arm Community". community.arm.com. Retrieved 26 April 2019.
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  25. ^ "Adopting the Arm Memory Tagging Extension in Android". Google Online Security Blog. Retrieved 6 August 2019.
  26. ^ "Arm A profile architecture update 2019". community.arm.com. Retrieved 26 September 2019.
  27. ^ "BFloat16 extensions for Armv8-A". community.arm.com. Retrieved 30 August 2019.
  28. ^ a b c "Arm releases SVE2 and TME for A-profile architecture – Processors blog – Processors – Arm Community". community.arm.com. Retrieved 25 May 2019.
  29. ^ a b "Arm SVE2 Support Aligning For GCC 10, LLVM Clang 9.0 – Phoronix". www.phoronix.com. Retrieved 26 May 2019.