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ARC (Argonaut RISC Core) embedded processors are a family of 32-bit central processing units (CPUs) originally designed by ARC International. They are widely used in System on a chip (SoC) devices for storage, home, mobile, automotive, and Internet of things (IoT) applications. ARC processors have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year.
ARC processors are now part of the Synopsys DesignWare series, and can be optimized for a wide range of uses. Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements. The ARC processors are also extendable, allowing designers to add their own custom instructions that can significantly increase performance or reduce power consumption.
ARC processors are reduced instruction set computing (RISC) processors, and employ the 16-/32-bit ARCompact instruction set architecture (ISA) that provides good performance and code density for embedded and host SoC applications. The processors are synthesizable and can be implemented in any foundry or process, and are supported by a complete suite of development tools.
Configuration of the ARC processors occurs at design time, using the ARChitect processor configurator. The core was designed to be extensible. Unlike most embedded microprocessors, extra instructions, registers and functionality can be added, in a modular fashion. Customers analyse the task, break down the operations, and then choose the appropriate extensions, or develop their own, to create their own custom microprocessor. They might optimise for speed, energy efficiency or code density. Extensions can include, for example, an memory management unit (MMU), a fast multiplier–accumulator, a USB Host, a Viterbi path decoder, or a user's proprietary RTL functions.
The ARC concept was developed initially within Argonaut Games through a series of 3D pipeline development projects starting with the Super FX chip for the Super Nintendo Entertainment System. In 1995, Argonaut was split into Argonaut Technologies Limited (ATL), which had a variety of technology projects, and Argonaut Software Limited (ASL). At the start of 1996, the General Manager of Argonaut, John Edelson, started reducing ATL projects such as BRender and motion capture and investing in the development of the ARC concept. In 1997, following investment by Apax Partners, ATL became ARC International and totally independent from Argonaut Games. Prior to their initial public offering on the London Stock Exchange, underwritten by Goldman Sachs and five other investment banks, three related technology companies were acquired: Metaware in Santa Cruz, California (development and modeling software), VAutomation in Nashua, New Hampshire (peripheral semiconductor IP), and Precise Software in Nepean, Ontario (RTOS).
Synopsys's DesignWare ARC Processor IP includes the ARC HS, ARC EM, ARC 700 and ARC 600 families of 32-bit processor cores, as well as the ARC AS211 and AS221 audio processors and optimized software audio codecs. ARC processor cores are based on a flexible and proven industry-standard instruction set architecture (ISA) with features optimized for a broad range of embedded and deeply embedded applications. The ARC processors feature:
- Performance-efficient designs deliver maximum performance while consuming a minimum amount of power and silicon area
- Highly configurable processors can be performance- and power-optimized for each instance on an SoC while sharing a common programming model
- Extensible ISA supports user-defined custom instructions, enabling integration of users' proprietary hardware to accelerate application-specific tasks
- Streamlined system integration through the ability to closely couple memory and directly map peripherals to the core, reduce system latency and cost
To accelerate the SoC development cycle, Synopsys's ARC Processor IP is supported by a complete and integrated development tool suite, including tools for configuration, software development and simulation. This enables ARC users to efficiently build, debug, profile and optimize their embedded software applications for ARC, while the available processor models makes it possible to get an early start on software development prior to hardware availability.
Synopsys offers a variety of simulation products spanning automatically-generated, cycle-accurate simulators to fast, functional instruction set simulators (ISS). Synopsys's simulation products enable software development prior to silicon being available.
DesignWare ARC xCAM is a 100% cycle-accurate simulator that is primarily used for hardware verification, but it can also be used to do final optimizations of critical software routines. The xCAM model is automatically generated from the processor configuration and can be used to evaluate different hardware scenarios.
- "Overcoming the power/performance paradox in processor IP". techdesignforums.com. Retrieved 2014-08-13.
- "Accelerating Development of Performance-Efficient SoCs". synopsys.com. Retrieved 2014-08-13.
- "ARChitect Processor Configurator". Arc.com. Retrieved 2014-03-02.
- Toshiba, ARC in configurable processor collaboration, 15 May 2006
- SPF: All About Power, Performance, 30 June 2006
- ARCHITECTURES: Programmable ARC platform targets low-cost multimedia, 2 October 2006
- ARC adopts clustered parallelism in media multiprocessing, 9 October 2006
- ARC signs "landmark" licensing deal with Intel, EE Times 9/11/2007