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|Designer||ARC International PLC|
|Encoding||Variable (16- and 32-bit)|
|Branching||Compare and branch|
|Extensions||APEX user-defined instructions|
|16 or 32 including SP user can increase to 60|
ARC processors are configurable and extensible for a wide range of uses in system on a chip (SoC) devices, including storage, digital home, mobile, automotive, and Internet of things (IoT) applications. They have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year.
ARC processors use reduced instruction set computing (RISC), and employ the 16-/32-bit ARCompact instruction set architecture (ISA) that provides good performance and code density for embedded and host SoC applications.
In 1995, Argonaut was split into Argonaut Technologies Limited (ATL), which had a variety of technology projects, and Argonaut Software Limited (ASL).
At the start of 1996, the General Manager of Argonaut, John Edelson, started reducing ATL projects such as BRender and motion capture and investing in the development of the ARC concept. In September 1996 Rick Clucas decided that the value of the ARC processor was in other people using it rather than Argonaut doing projects using it and asked Bob Terwilliger to join as CEO; Rick Clucas then took on the role of CTO.
In 1997, following investment by Apax Partners, ATL became ARC International and totally independent from Argonaut Games. Prior to their initial public offering on the London Stock Exchange, underwritten by Goldman Sachs and five other investment banks, three related technology companies were acquired: Metaware in Santa Cruz, California (development and modeling software), VAutomation in Nashua, New Hampshire (peripheral semiconductor IP), and Precise Software in Nepean, Ontario (RTOS).
In April 2020 Synopsys released the ARCv3 ISA with 64-bit support.
Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements.
Configuration of the ARC processors occurs at design time, using the ARChitect processor configurator. The core was designed to be extensible, allowing designers to add their own custom instructions that can significantly increase performance or reduce power consumption.
Unlike most embedded microprocessors, extra instructions, registers, and functionality can be added in a modular fashion. Customers analyse the task, break down the operations, and then choose the appropriate extensions, or develop their own, to create their own custom microprocessor. They might optimise for speed, energy efficiency or code density. Extensions can include, for example, a memory management unit (MMU), a fast multiplier–accumulator, a USB host, a Viterbi path decoder, or a user's proprietary RTL functions.
- "Overcoming the power/performance paradox in processor IP". techdesignforums.com. Retrieved 13 August 2014.
- ARC Acquires MetaWare Archived 21 July 2020 at the Wayback Machine, www.edn.com, 1999-09-27
- Synopsys Introduces New 64-bit ARC Processor IP
- "ARChitect Processor Configurator". Arc.com. Archived from the original on 22 April 2009. Retrieved 2 March 2014.
- "Accelerating Development of Performance-Efficient SoCs". synopsys.com. Archived from the original on 4 December 2016. Retrieved 13 August 2014.
- Toshiba, ARC in configurable processor collaboration, 15 May 2006
- SPF: All About Power, Performance, 30 June 2006
- ARCHITECTURES: Programmable ARC platform targets low-cost multimedia, 2 October 2006
- ARC adopts clustered parallelism in media multiprocessing, 9 October 2006
- ARC signs "landmark" licensing deal with Intel, EE Times 9/11/2007