|Designed by||ARM Holdings|
|L1 cache||80 KiB (48 KiB I-cache with parity, 32 KiB D-cache with ECC) per core|
|L2 cache||512 KiB to 2 MiB|
|Architecture and classification|
|Products, models, variants|
|Product code name(s)|
The ARM Cortex-A57 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline. It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
- Pipelined processor with deeply out of order, speculative issue 3-way superscalar a lined with pipeline
- DSP and NEON SIMD extensions are mandatory per core
- VFPv4 Floating Point Unit onboard (per core)
- Hardware virtualization support
- Thumb-2 instruction set encoding reduces the size of 32-bit programs with little impact on performance.
- TrustZone security extensions
- Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution
- 32 KiB data (2-way set-associative) + 48 KiB instruction (3-way set-associative) L1 cache per core
- Integrated low-latency level-2 (16-way set-associative) cache controller, 512 KB, 1 MB, or 2 MB configurable size per cluster
- 48-entry fully associative L1 instruction Translation Lookaside Buffer (TLB) with native support for 4 KiB, 64 KiB, and 1 MB page sizes
- 4-way set-associative of 1024-entry L2 TLB
- 2-level dynamic predictor with Branch Target Buffer (BTB) for fast target generation
- Static branch predictor
- Indirect predictor
- Return stack
In January 2014, AMD announced the Opteron A1100. Intended for servers, the A1100 has four or eight Cortex-A57 cores, support for up to 128 GiB of DDR3 or DDR4 RAM, an eight-lane PCIe controller, eight SATA (6 Gbit/s) ports, and two 10 Gigabit Ethernet ports. The A1100 series was released in January 2016, with four and eight core versions.
- "Cortex-A57 Processor". ARM Holdings. Retrieved 2014-02-02.
- Anand Lal Shimpi (January 28, 2014). "It Begins: AMD Announces Its First ARM Based Server SoC, 64-bit/8-core Opteron A1100". Anandtech. Retrieved 2014-02-02.
- "Welcome to AMD - Processors - Graphics and Technology - AMD". Amd.com. Retrieved 10 December 2018.
- Valich, Theo (14 January 2016). "AMD finally Launches K12, ARM-based Opteron". Vrworld.com. Retrieved 10 December 2018.
- "Snapdragon 810 Processors". Qualcomm. Retrieved 2015-02-18.