Active State Power Management

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Active-state power management (ASPM) is a power management mechanism for PCI Express devices to garner power savings while otherwise in a fully active state. Predominantly, this is achieved through active-state link power management; i.e., the PCI Express serial link is powered down when there is no traffic across it. It is normally used on laptops and other mobile Internet devices to extend battery life.

As serial-based PCI Express devices, become less active, it is possible for the computer's power management system to take the opportunity to reduce overall power consumption by placing the link PHY into a low-power mode and instructing other devices on the link to follow suit. This is usually managed by the operating system's power management software or through the BIOS, thus different settings can be configured for laptop battery mode versus running from the battery charger. Low power mode is often achieved by reducing or even stopping the serial bus clock as well as possibly powering down the PHY device itself.

While ASPM brings a reduction in power consumption, it can also result in increased latency as the serial bus needs to be 'woken up' from low-power mode, possibly reconfigured and the host-to-device link re-established. This is known as ASPM exit latency and takes up valuable time which can be annoying to the end user if it is too obvious when it occurs. This may be acceptable for mobile computing, however, when battery life is critical.

Currently, two low power modes are specified by the PCI Express 2.0 specification; L0s and L1 mode. L0s concerns setting low power mode for one direction of the serial link only, usually downstream of the PHY controller. L1 shuts off PCI Express link completely, including the reference clock signal, until a dedicated signal (CLKREQ#) is asserted, and results in greater power reductions though with the penalty of greater exit latency.

See also[edit]

External links[edit]

  • "PCI Express Specifications". PCI-SIG.
  • "ASPM Optionality (affecting PCIe Base Specification Revision 2.1)" (PDF). PCI-SIG. 2009-06-19. Archived from the original (PDF) on 2016-06-27. Retrieved 2016-07-16.