Advanced Synchronization Facility

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Advanced Synchronization Facility (ASF) is a proposed extension to the x86-64 instruction set architecture that adds hardware transactional memory support. It was introduced by AMD; the latest specification was dated March 2009.[1] As of October 2013, it was still in the proposal stage.[2] No released microprocessors implement the extension.


ASF provides the capability to start, end and abort transactional execution and to mark CPU cache lines for protected memory access in transactional code regions. It contains four new instructions—SPECULATE, COMMIT, ABORT and RELEASE—and turns the otherwise invalid LOCK-prefixed MOVx, PREFETCH and PREFETCHW instructions into valid ones inside transactional code regions. Up to 256 levels of nested transactional code regions is supported.

The SPECULATE and COMMIT instructions mark the start and end of a transactional code region. Inside transactional code regions, the LOCK-prefixed MOVx reg/xmm, mem, PREFETCH and PREFETCHW instructions can mark up to four cache lines for protected memory access. Accesses from other processor cores to the protected cache lines result in exceptions, which in turn cause transaction aborts. Stores to protected cache lines must be performed using the LOCK MOVx mem, reg/imm/xmm instructions. Marked cache lines can be released from protection with the RELEASE instruction. Transaction aborts generated by hardware or explicitly requested through the ABORT instruction rolls back modifications to the protected cache lines and restarts execution from the instruction following the top-level SPECULATE instruction.

See also[edit]


  1. ^ "Advanced Synchronization Facility Proposed Architectural Specification" (PDF). AMD. Mar 2009. Retrieved 2013-10-27.
  2. ^ "AMD 'Advanced Synchronization Facility' Proposal". AMD. Archived from the original on 2013-11-13. Retrieved 2013-10-27.