|Products||Active-HDL, ALINT, Riviera-PRO, Spec-TRACER, HES-DVM, HES-7|
Aldec, Inc. is a privately owned electronic design automation company, and provides software and hardware used in creation and verification of digital designs targeting FPGA and ASIC technologies. Headquartered in Henderson, Nevada, Aldec also has offices/development centers in Europe(UK), Japan, Israel, India, China, Taiwan, Poland and Ukraine.
As a member of Accellera and IEEE Standards Association Aldec actively participates in the process of developing new standards and updating existing standards (e.g. VHDL, SystemVerilog).
Aldec provides HDL simulation engine for other EDA tools (e.g. Altium Designer) and bundles special version of its tools with FPGA vendors software (e.g. Lattice).
- Aldec was founded in 1984 by Dr. Stanley M. Hyduke.
- In 1985 the company released its first product: MS-DOS-based gate-level simulator SUSIE. For the next couple of years several versions of the product were used as companion simulators for popular schematic entry tools such as OrCAD.
- Sensing growing popularity of Microsoft Windows, ALDEC ported its simulator to this platform and added schematic entry and design management tool. The new software suite was released in 1992 as Active-CAD (some low-end versions of the suite were for some time sold under Susie-CAD brand). One of the distinguishing features of Active-CAD was the ability of instantaneous transfer of schematic changes to the simulator, allowing quick verification of the behavior of the modified circuit.
- In 1996 Aldec signed agreement with Xilinx that allowed distribution of Xilinx-only version of Active-CAD under the Foundation name.
- While VHDL and Verilog were supported by Active-CAD in the form of schematic macros, the release of Active-VHDL in 1997 marked the shift from netlist-based design to HDL-based design. After adding Verilog support, Active-VHDL was renamed to Active-HDL and is still available (as of 2007).
- In 2000 ALDEC released high-performance HDL simulator working not only on Windows, but also on Solaris and Linux platforms.
- In 2001 ALDEC added hardware to its product line: HES Platform that allows hardware acceleration of HDL simulation and incremental prototyping of hardware.
- Year 2003 marks the release of Riviera supporting assertion based verification (OpenVera, PSL and SystemVerilog can be used to write properties, assertions and coverage.)
- Support for SystemC and non-assertion part of SystemVerilog was added in 2004. Interfaces to MATLAB and Simulink appeared in Aldec tools for the first time in 2005.
- Stimulated by requests from Verilog users, ALDEC released in 2007 an advanced, user-configurable lint tool implementing rules created by STARC - Japanese consortium of major silicon vendors.
- Active-HDL - FPGA development environment built around common kernel HDL simulator. Supports text-based and graphical design entry and debugging tools, allows mixed-language simulation (VHDL/Verilog/EDIF/SystemC/SystemVerilog) and provides unified interface to various synthesis and implementation tools. Also supports assertion based verification with Open Vera, PSL, or Systemverilog Assertion statements. Special versions of the software that support just one FPGA vendor are available, e.g. Active-HDL Lattice Edition. Only available on MS Windows platform.
- Riviera-PRO - high-end HDL simulator targeting ASIC and large FPGA designs. Riviera extends Active-HDL's simulation features with support for advanced verification methodologies such as linting, functional coverage, OVM and UVM, hardware acceleration, and prototyping. Riviera-PRO is a new generation of the tool known as Riviera-Classic and is available in 32-bit and 64-bit on MS Windows and Linux.
- HES-DVM - solution allowing acceleration of HDL simulation (10x to 50x verification time reduction), emulation of the entire design and hardware/software co-simulation (useful in Embedded System development).
- ALINT - dedicated design rule checker/linting tool. ALINT is able to conduct extensive textual analysis of individual Verilog and VHDL sources and advanced checks of the entire design hierarchy. Multiple sets of highly configurable, predefined rules are available and new, custom rules can be created using provided API. Built-in Phase-Based Linting methodology allows faster, more efficient checking of rules.
- Spec-TRACER - unified requirements life-cycle management application designed specifically for FPGA and ASIC designs. Facilitates requirements capture, management, analysis, traceability and reporting; integrates with Windows-based HDL design and simulation tools.
- IP Products - a set of general-purpose Intellectual Property blocks created by Aldec and its partners, validated in Active-HDL and Riviera environments.
- HES-7 - high capacity, high density, FPGA-based ASIC prototyping solution. With help of Xilinx Virtex-7 FPGA-based prototyping boards, HES-7 allows testing designs of up to 24 million ASIC gates.
- Microsemi RTAX/RTSX Prototyping - the efficient way of prototyping designs with radiation hardened FPGA by using footprint-compatible prototyping boards with flash-based, reprogrammable chips on top. The solution includes optional software for netlist translation.
- DO-254 Compliance Tool Set (CTS) - It is a complete verification solution that can assure the FPGA on your system to be DO-254/ED80 compliant. The CTS gives the user the ability to perform an advanced way of In-Hardware Simulation instead of the traditional Hardware Testing. As test vectors for the In-Hardware Simulation, you can reuse the same testbench with 100% Code Coverage results captured from RTL simulation. By reusing the same testbench, the Hardware Verification can easily achieve requirements traceability. You can perform the In-Hardware Simulation at speed at the target device. The CTS also allows easy comparison and debugging of the In-Hardware Simulation and HDL Simulation results via waveform format.
Aldec also offers a special Student-Edition of Active-HDL, downloadable from Aldec's website. The Student-Edition has limited design capacity and some reduction of program functionality, but supports both design languages (Verilog/VHDL.)
- EETimes News,"Aldec FPGA simulation added to Altium Designer", EETimes.com, 2010/5/25
- EN-genius Programmable logic ZONE, "Lattice And Aldec Form Alliance For FPGA Design And Design Verification"
- Richard Goering, "Aldec rolls out Linux-based mixed-language simulator", EETimes.com, November 13, 2000
- Christine Evans-Pughe, "Protecting your IP just got simpler", Paragraph 11, Electronics Weekly, October 13, 2006
- ECE-UNLV staff, "ALDEC, (...) plays a significant role in ECE programs", Page 3, ECE-UNLV News, Vol 5, 2005
- EDN Online Staff, "EDA Software Sold in Walmart.", EDN, February 20, 2006