Alliant Computer Systems

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Alliant Computer Systems Corporation
Founded1982; 41 years ago (1982)
Defunct1992 (1992)
HeadquartersLittleton, Massachusetts, United States

Alliant Computer Systems Corporation was a computer company that designed and manufactured parallel computing systems. Together with Pyramid Technology and Sequent Computer Systems, Alliant's machines pioneered the symmetric multiprocessing market. One of the more successful companies in the group, over 650 Alliant systems were produced over their lifetime. The company was hit by a series of financial problems and went bankrupt in 1992.



Alliant was founded, as Dataflow Systems, in May 1982 by Ron Gruner, Craig Mundie and Rich McAndrew[1] to produce machines for scientific and engineering users who needed smaller, less costly machines than offerings from Cray Computer and similar high-end vendors. Machines that addressed this market segment later became known as minisupercomputers. At the time there was a huge gap on the price/performance curve as a highly configured VAX 11/780 had a performance of about a MIP and MegaFLOP for around $1M USD and a Cray-1S or Cray 1M over $10M USD.

Alliant's first machines were announced in 1985, starting with the FX series. The FX series consisted of four types of 18" x 18" boards: Computational Elements, or CEs, System Cache, Interactive Processor (IP) Cache, and Memory Modules. Each board plugged into a backplane using a special high density connector. The caches and memory modules all communicated with each other over a 2 x 64 bit bus called the DMB (Dataflow Memory Bus). The backplane was an active backplane and it contained an 8 x 4 crossbar switch (FX/8) that allowed any CE to connect to one of four cache ports, two on each System Cache. Total cache bandwidth was 376 MB/s.

The CEs included a set of Weitek 1064/1065 FPU's and several custom designed support chips to implement a custom vector processor. The scalar instruction set was based upon the popular Motorola 68000 architecture. The floating point instruction set, vector instruction set, and concurrency instruction set were all custom co-processor instruction sets designed by Alliant. The shared system cache and a special concurrency bus implemented low latency concurrency control that could be exploited automatically by high level language compilers to provide data-parallel processing among the CEs. The scalar instruction cycle time for the original CE was 170 ns, the vector processor was twice as fast as the scalar processor with a cycle time of 85 ns.

Each IP Cache had three ports that connected via ribbon cables to Interactive Processors, IPs, which used Motorola 68012's and, subsequently Motorola 68020's and then Motorola 68030's with 4 MB of local RAM in a Multibus form factor plugged into a 13 slot Multibus chassis.

Memory modules were 8 MB each and four way interleaved with ECC. Read bandwidth was 188 MB/s.

Like many early multiprocessing systems, the FX series ran a version of 4.2 BSD Unix on the IPs and CEs, known as Concentrix which initially added multiprocessor support and new VM and IO sub-systems. Subsequent releases added features such as the first striped Track File System (TFS) and support for real time scheduling (FX/RT).

Systems were numerated for the largest potential number of CEs inside, the FX/1, FX/4 and FX/8. Alliant machines were fairly small, the FX/1 was about the size of a large full-height PC, while the FX/8 was smaller than a VAX-11/780, about the size of a large photocopier. All the systems were air cooled. The speed of an FX/1 was about 2.5 MIPS (million instructions per second) and compared favorably to the 1 MIPS VAX-11/780. A fully populated eight CE FX/8, with eight times the aggregate MIPS, was in practice around five times faster than the FX/1 at solving problems that allowed a high degree of parallel computation (see Amdahl's law).

A second series of FX machines, introduced in early 1988, replaced the CE with pin compatible new custom hardware known as the Advanced Computational Element (ACE). The Weitek FPUs were replaced by a floating point chipset made by Bipolar Integrated Technology which formed the core of a redesigned vector processor with 32 64-bit vector elements, 8 64-bit scalar floating point registers, 8 32-bit integer registers, and 8 32-bit address registers. The new vector processor increased vector processing speed by reducing the in-register cycle time to 42 ns. The scalar instruction cycle time, cache and memory bandwidth remained the same. The ACE, with its higher level of integration using more advanced ASICs, also required less printed circuit board space allowing it to return to the 18x18 inch square profile used by the other system boards in the main chassis. These were used in the FX/40, FX/80 and VFX machines. In addition, because of the pin compatibility, existing FX/4 and FX/8 systems could be field upgraded to FX/40 and FX/80 configurations by simple replacement of CE's with ACE's along with an update to the microcode file on the system disk. However systems of mixed configurations of CEs and ACEs were not supported. The smaller FX/1, because of restrictions in chassis cooling, could not be upgraded.

Alliant offered a number of software packages for its machines, including a solver for linear equations (FX/Skyline Solver), a C compiler (FX/C compiler), and scientific libraries (FX/Linpack and FX/Eispack).[2]


In 1990, the FX/2800 series replaced the CE/ACEs and IPs with modules based on the Intel i860 RISC chip. The i860 was an early superscalar CPU that allowed the programmer access directly into the pipelines; with custom coding the 860 was a very fast system, making it perfect for supercomputer applications. In the new series the Super Computational Element (SCE) and Super Interactive Processor (SIP) both consisted of up to four i860s, up to seven of which could be interconnected on the crossbar. A fully expanded FX/2800 could support 28 i860's in total.

Also in July 1988 Alliant purchased Raster Technologies,[3] a provider of high-resolution graphics terminals and custom graphics cards for Sun Microsystems workstations. Their GX4000 product was a combination of PHIGS+ software and special graphical boards that could generate and display graphical vectors very fast. For 3D effects, a hardware Z-buffer was available. The Raster graphics technology was integrated with FX/40 and FX/80 machines to produce the VFX, Alliant's first fully integrated graphical minisupercomputer.

Alliant's final product series was the CAMPUS/800, a massively parallel machine based on units similar to the FX/2800 known as ClusterNodes and sharing a total of up to 4GB of unified memory. Each ClusterNode was connected to up to 32 others with an intra-ClusterNode switch, with a latency of 1 µs and 1.12 GB/s bandwidth. An inter-ClusterNode switch based on HIPPI was also available, with a latency of 30 µs and 2.56 GB/s bandwidth. The largest CAMPUS system created included 192 ClusterNodes in total, and provided 4.7 GFLOPS.

The CAMPUS/800 was first announced in 1991, but the company was hit by a series of financial problems and went bankrupt in 1992. Various Alliant systems soldiered on in service for many years after that however, and were generally considered very reliable.

Alliant also contributed to the development of High Performance Fortran.[4]: 7–9 

The Computer History Museum has examples of the FX/8 and FX/1 (from Convex Computer Corporation after Alliant's fall), but is seeking examples of FX/80 and FX/2800 configurations.


  1. ^ Livingston, Jessica (1 November 2008). Founders at Work: Stories of Startups' Early Days. Apress. p. 427. ISBN 978-1-4302-1077-1.
  2. ^ Gibson, Stanley (2 November 1987), "Alliant adds compiler tools", Computerworld, IDG Enterprise, vol. 21, no. 44, p. 29, ISSN 0010-4841
  3. ^ Architecture Technology Corporation (September 1991). Minisupercomputers. Elsevier Science. p. 61. ISBN 978-1-4832-9554-1. In July, 1988, Alliant acquired Raster Technologies.
  4. ^ Kennedy, Ken; Koelbel, Charles; Zima, Hans (2007). The rise and fall of High Performance Fortran. HOPL III: 3rd ACM SIGPLAN conference on History of programming languages. pp. 7-1–7-22. doi:10.1145/1238844.1238851. ISBN 978-1-59593-766-7.