BBN Butterfly

From Wikipedia, the free encyclopedia
Jump to: navigation, search

The BBN Butterfly was a massively parallel computer built by Bolt, Beranek and Newman in the 1980s. It was named for the "butterfly" multi-stage switching network around which it was built. Each machine had up to 512 CPUs, each with local memory, which could be connected to allow every CPU access to every other CPU's memory, although with a substantially greater latency (roughly 15:1) than for its own. The CPUs were commodity microprocessors. The memory address space was shared.

The first generation used Motorola 68000 processors, followed by a 68010 version.[1] The Butterfly connect was developed specifically for this computer. The second or third generation, GP-1000 models used Motorola 68020's and scaled to 256 CPUs. The later, TC-2000 models used Motorola MC88100's, and scaled to 512 CPUs.[2]

The Butterfly was initially developed as the Voice Funnel, a router for the ST-II protocol intended for carrying voice and video over IP networks. The Butterfly hardware was later used for the Butterfly Satellite IMP (BSAT) packet switch of DARPA's Wideband Packet Satellite Network which operated at multiple sites around the US over a shared 3 Mbps broadcast satellite channel.[3] In the late 1980s, this network became the Terrestrial Wideband Network, based on terrestrial T1 circuits instead of a shared broadcast satellite channel and the BSAT became the Wideband Packet Switch (WPS). Another DARPA sponsored project at BBN produced the Butterfly Multiprocessor Internet Gateway (Internet Router) to interconnect different types of networks at the IP layer. Like the BSAT, the Butterfly Gateway broke the contention of a shared bus minicomputer architecture that had been in use for Internet Gateways by combining the routing computations and I/O at the network interfaces and using the Butterfly's switch fabric to provide the network interconnections. This resulted in significantly higher link throughputs. [4]

The Butterfly began with a proprietary operating system called Chrysalis, but moved to a Mach kernel operating system in 1989. While the memory access time was non-uniform, the machine had SMP memory semantics, and could be operated as a symmetric multiprocessor.[citation needed]

The largest configured system with 128 processors was at the University of Rochester Computer Science Department.[5] Most delivered systems had about 16 processors. No known configurations appear to be in museums. At least one system is thought to be sitting within a DARPA autonomous vehicle.[citation needed]

TotalView, the parallel program debugger developed for the Butterfly, outlived the platform and was ported to a number of other massively parallel machines.

See also[edit]

  • Pluribus was an earlier multiprocessor designed at BBN.

References[edit]

  1. ^ Rettberg, R; Wyman, С; Hunt, D.; Hoffman, M.; Carvey, P.; Hyde, B.; Clark, W.; Kraley, M. (August 1979). "Development of a Voice Funnel". System: Design Report. Bolt Beranek and Newman Inc. Report No. 4098. 
  2. ^ Amestoy, Patrick R.; Daydé, Michel J.; Duff, Iain S.; Morère, Pierre (October 9, 1992), "Linear Algebra Calculations on a virtual shared memory computer", Int Journal of High Speed Computing (published 1992), 7, pp. 21–43, CiteSeerX 10.1.1.37.8448Freely accessible 
  3. ^ Edmond, Winston; Blumenthal, Steven; Echenique, Andres; Storch, Steven; Calderwood, Tom; Rees, Tom (August 6, 1986), "The ButterflyTM Satellite IMP for the Wideband Packet Satellite Network", ACM SIGCOMM, Stowe, VT (published 1986), pp. 194 – 202 
  4. ^ Partridge, Craig; Blumenthal, Steven (January 2006). "Data Networking at BBN". IEEE Annals of the History of Computing. Washington, DC: IEEE Computer Society. 28 (1): 56–71. 
  5. ^ Leblanc, T. J.; Scott, M.L.; Brown, C.M. (September 1, 1988), Large-Scale Parallel Programming: Experience with the BBN Butterfly Parallel Processor, University of Rochester Computer Science Department 

External links[edit]