CPUs using CMOS were released from 1986 (e.g. 12 MHz Intel 80386). As CMOS transistor dimensions were shrunk the clock speeds also increased. Since about 2004 CMOS CPU clock speeds have leveled off at about 3.5 GHz.
- 22nm Ivy Bridge in 2012
- first 14 nanometer processors shipped in Q4 2014.
- In May 2015, Samsung Electronics showed a 300 mm wafer of 10 nm FinFET chips.
Comparisons of technology
Nikonov benchmarked (theoretically) many technologies in 2012, and updated it in 2014. The 2014 benchmarking included 11 electronic, 8 spintronic, 3 orbitronic, 2 ferroelectric, and 1 straintronic technology.
Some areas of investigation
- tunnel junction devices, eg Tunnel field-effect transistor
- indium antimonide transistors
- carbon nanotube FET, eg CNT Tunnel field-effect transistor
- graphene nanoribbons
- molecular electronics
- spintronics — many variants
- future low-energy electronics technologies, ultra-low dissipation conduction paths, including
- photonics and optical computing
- superconducting computing
- rapid single-flux quantum (RSFQ)
Superconducting computing and RSFQ
Superconducting computing includes several beyond-CMOS technologies that use superconducting devices, namely Josephson junctions, for electronic signals processing and computing. One variant called rapid single-flux quantum (RSFQ) logic was considered promising by the NSA in a 2005 technology survey despite the drawback that available superconductors require cryogenic temperatures. More energy-efficient superconducting logic variants have been developed since 2005 and are being considered for use in large scale computing.
- International Technology Roadmap for Semiconductors
- International Roadmap for Devices and Systems
- Moore's law
- MOSFET scaling
- Nanostrain, a project to characterise piezoelectric materials for low power switches
- S-PULSE, the EU Shrink-Path of Ultra-Low Power Superconducting Electronics initiative
- Probabilistic complementary metal-oxide semiconductor (PCMOS)
- Extending the road beyond CMOS. Hutchby 2002
- Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking. Ver.3.4 09/21/2012
- Bernstein; et al. (2011). "Device and Architecture Outlook for Beyond CMOS Switches". Cite journal requires
- "Review of Advanced and Beyond CMOS FET Technologies for Radio Frequency Circuit Design. Carta 2011" (PDF). Archived from the original (PDF) on 2015-02-23. Retrieved 2015-02-23.
- Power-constrained CMOS scaling limits. Frank 2002[permanent dead link]
- "Samsung vows to start 10nm chip production in 2016". 23 May 2015. Retrieved 16 July 2015. CS1 maint: discouraged parameter (link)
- Nikonov and Young (2015). "Benchmarking of Beyond-CMOS Exploratory – Devices for Logic Integrated Circuits". IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. 1: 3–11. Bibcode:2015IJESS...1....3N. doi:10.1109/JXCDC.2015.2418033.
- ITRS 2015 Beyond CMOS
- Seabaugh (September 2013). "The Tunneling Transistor". IEEE.
- Holmes DS, Ripple AL, Manheimer MA (2013). "Energy-efficient superconducting computing—power budgets and requirements", IEEE Trans. Appl. Supercond., vol. 23, 1701610, June 2013.
- Holmes DS, Kadin AM, Johnson MW (2015). "Superconducting Computing in Large-Scale Hybrid Systems", Computer, vol. 48, pp. 34–42.