Bit-serial architecture

From Wikipedia, the free encyclopedia
Jump to navigation Jump to search

In digital logic applications, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel word architectures, in which data values are sent all bits or a word at once along a group of wires.

All digital computers built before 1951, and most of the early massive parallel processing machines used a bit-serial architecture—they were serial computers.

Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.[1]

Often N serial processors will take less FPGA area and have a higher total performance than a single N-bit parallel processor.[2]

See also[edit]


  1. ^ Denyer, Peter B.; Renshaw, David (1985). VLSI signal processing: a bit-serial approach. VLSI systems series. Addison-Wesley. ISBN 978-0-201-13306-6.
  2. ^ Raymond J. Andraka. "Building a High Performance Bit Serial Processor in an FPGA".

External links[edit]