|Discontinued||October 22nd, 2013|
|Designed by||IBM and Nintendo|
|Max. CPU clock rate||729 MHz|
|L1 cache||32/32 kB|
|L2 cache||256 kB|
|Architecture and classification|
|Technology node||90 nm (2006-2007), 65 nm (2007-2013)|
|Instruction set||PowerPC (PowerPC ISA 1.10)|
|Products, models, variants|
|POWER, PowerPC, and Power ISA architectures|
|NXP (formerly Freescale and Motorola)|
|Cancelled in gray, historic in italic|
Broadway is the codename of the 32-bit central processing unit (CPU) used in Nintendo's Wii home video game console. It was designed by IBM, and was initially produced using a 90 nm SOI process and later produced with a 65 nm SOI process.
Broadway was produced by IBM at their 300 mm semiconductor development and manufacturing facility in East Fishkill, New York. The bond, assembly, and test operation for the Broadway module is performed at the IBM facility in Bromont, Quebec. Very few official details have been released to the public by Nintendo or IBM. Unofficial reports claim it is derived from the 486 MHz Gekko architecture used in the GameCube and runs 50% faster at 729 MHz.
The PowerPC 750CL, released in 2006, is a stock CPU offered by IBM and virtually identical to Broadway. The only difference is that the 750CL came in variants, ranging from 400 MHz up to 1000 MHz.
- 90 nanometer process technology, shrunk to 65 nm in 2007. 
- Superscalar Out-of-order execution PowerPC core, specially modified for the Wii platform
- IBM silicon on insulator (SOI) technology
- Backward compatible with the Gekko processor
- 729 MHz
- 4 stages long Two integer ALUs (IU1 and IU2) – 32 bit
- 7 stages long 64-bit floating-point unit (FPU) (or 2 × 32-bit SIMD, often found under the denomination "paired singles")
- Branch Prediction Unit (BPU)
- Load-Store Unit (LSU)
- System Register Unit (SRU)
- Memory Management Unit (MMU)
- Branch Target Instruction Cache (BTIC)
- SIMD Instructions – PowerPC750 + Roughly 50 new SIMD instructions, geared toward 3D graphics
- 64 kB L1 cache (32 kB instruction + 32 kB data)
- 256 kB L2 cache
- 2.9 GFLOPS
- 243 MHz
- 1.944 gigabytes per second bandwidth
- IBM (2006). "IBM Ships First Microchips for Nintendo's Wii Video Game System". Retrieved 2006-09-08.
- "Wii Technical Specification, Wii". Archived from the original on 2011-08-10. Retrieved 2009-05-29.
- "IBM Broadway RISC Microprocessor User's Manual, v0.6" (PDF). p. 61. Archived from the original (PDF) on 2013-12-04.
- "IBM PowerPC 750CL Microprocessor Revision Level DD2.x" (PDF). Archived from the original (PDF) on 2013-06-03.
- "IBM PowerPC 750CL RISC Microprocessor User's Manual" (PDF). Archived from the original (PDF) on 2012-11-15.
- "Wii U CPU |Espresso| die Photo - Courtesy of Chipworks".