Bus Functional Model

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A Bus Functional Model or BFM (also known as a Transaction Verification Models or TVM) is a non-synthesizable software model of an integrated circuit component having one or more external buses. The emphasis of the model is on simulating system bus transactions prior to building and testing the actual hardware. BFM's are usually defined as tasks in Hardware description languages (HDLs), which applies stimulus to the design under test/verification via complex waveforms and protocols. A BFM is typically written in an HDL language such as verilog, VHDL, SystemC, or SystemVerilog.

On one side, it drives and samples low-level signals according to the bus protocol. On the other side, tasks are available to create and respond to bus transactions.

BFMs are often used as reusable building blocks to create simulation test benches, where the signal ports on a design under test are connected to the appropriate BFMs in the testbench for the purpose of simulation.

For instance , let's say if you're a design house and you have the requirement of buying an IP from a 3rd party source, the 3rd part IP provider might give you a C model for verification whereas the actual IP would only go to the foundry.

BFMs' thus are used as substitute models for better IP protection.

Earlier, BFM were treated as a non-synthesizable entity but over the period of time BFMs are also available as synthesizable models as well.

Transaction Verification Models[edit]

BFMs are sometimes referred to as TVMs or Transaction Verification Models. This is to emphasize that bus operations of the model have been bundled into atomic bus transactions to make it easier to issue and view bus transactions. Viewing of bus transactions of TVMs is similar to viewing the output of a protocol analyzer or bus sniffer.


  • Mitchel, Donna (2001). "Manual and Automatic VHDL/Verilog Test Bench Coding Techniques" (PDF). Dedicated Systems Magazine. 9 (2). Archived from the original (PDF) on 22 January 2004. Retrieved 8 April 2013.