Cadence Design Systems
Cadence R&D center
|Traded as||NASDAQ: CDNS|
|Industry||Software & Programming|
|Headquarters||San Jose, California, United States|
|Lip-Bu Tan, President/CEO|
|Revenue||1.702 billion USD (2015)|
|$252 million USD (2015)|
Number of employees
|6786 (April 2, 2016)|
Cadence Design Systems, Inc (NASDAQ: CDNS) is an American multinational electronic design automation (EDA) software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software and hardware for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Cadence Design Systems, headquartered in San Jose, California, is a supplier of electronic design technologies and engineering services in the electronic design automation (EDA) industry. The company develops software used to design chips and printed circuit boards, as well as intellectual properties (IP) covering a broad range of areas, including interfaces, memory, analog, SoC peripherals, dataplane processing units, and verification.
Cadence products primarily target FPGA and ASIC design engineers, and are used to move a design into packaged silicon (ASIC), with products for custom and analog design, digital design, mixed-signal design, verification, and package/PCB design.
To help integrate, verify, and implement complex digital SoCs, there are solutions that encompass design IP, timing analysis and signoff, services, and tools and methodologies. The company also provides products that assist with the development of complete hardware and software platforms that support end applications.
Cadence Design Systems was the result of a merger perfected in 1988 of Solomon Design Automation (SDA), co-founded in 1983 by Richard Newton, Alberto Sangiovanni-Vincentelli and James Solomon, and ECAD, co-founded by Glen Antle and Paul Huang in 1982. Joseph Costello was appointed as CEO from 1988–1997, and Cadence became the largest EDA company during his tenure.
On October 15, 2008, Cadence President and CEO Michael Fister and four other top executives resigned, namely Executive Vice President of Worldwide Field Operations Kevin Bushby, Executive Vice President of Products and Technologies Organization James S. Miller Jr., Executive Vice President and Chief Administrative Officer William Porter and Executive Vice President of Corporate Affairs R. L. Smith McKeithen. This was followed by a large layoff of 20% to 25% of Cadence's employees.
In January 2009, the company announced the appointment of Lip-Bu Tan as President and CEO. Tan was most recently CEO of Walden International, a venture capital firm, and remains chairman of the firm. He has served on the Cadence Board of Directors since 2004, where he served on the Technology Committee for four years.
In 2009, Cadence announced that they would lay-off 225 employees, and new CEO Lip-Bu Tan voluntarily reduced his salary by 20%; Cadence's senior vice-presidents and Board Members took a pay cut of 10%.
In January 2010, Cadence laid-off an additional 120 workers.
At the end of 2013, the company employed more than 5,200 people and reported 2013 revenues of approximately $1.46 billion. In November 2007 Cadence was named one of the "50 Best Places to Work in Silicon Valley" by San Jose Magazine.
Cadence's product offerings are targeted at various types of design and verification tasks which include:
- Virtuoso Platform - Tools for designing full-custom integrated circuits; includes schematic entry, behavioral modeling (Verilog-AMS), circuit simulation, custom layout, physical verification, extraction and back-annotation. Used mainly for analog, mixed-signal, RF, and standard-cell designs, but also memory and FPGA designs.
- Encounter Platform - Tools for implementation of digital integrated circuits. This includes floorplanning, test, place and route and clock tree synthesis. Typically a digital design implementation starts from Verilog netlists from the synthesized design. Includes Nanoroute technology in the routing stage.
- Incisive Platform - Tools for simulation and functional verification of RTL including Verilog, VHDL and SystemC based models. Includes formal verification, formal equivalence checking, hardware acceleration, and emulation.
- Palladium series - Accelerators and emulators for hardware and software co-verification and system-level verification.
- Design IP - Cadence provides design IP targeting areas including memory (DRAM), covering DDR1, DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4, and Wide I/O; storage (non-volatile memory), covering NVM Express and NAND Flash controller and PHY; and high-performance interface protocols such as PCI Express Gen3, 40/100G Ethernet, and USB 2 and USB 3.
- Verification IP (VIP) - Cadence provides the broadest set of commercial VIP available with over 30 protocols in its VIP Portfolio. They include AMBA, PCI Express, USB, SATA, OCP, SAS, MIPI and many others. Cadence VIP also provides the unique Compliance Management System (CMS) to automate protocol compliance verification.
- Integration Optimized IP (Design IP) - Cadence offers Vertically Integrated IP, inclusive of Digital Controller, Serdes Layer, and Device Driver. Protocols supported include USB, DDR, PCI-Express, 10G-40G Ethernet, and On Chip Bus Fabric.
- Allegro Platform - Tools for co-design of integrated circuits, packages, and PCBs.
- OrCAD/PSpice - Tools for smaller design teams and individual PCB designers.
- Sigrity technologies - Tools for signal and power verification for system-level signoff verification and interface compliance.
- Since the acquisition of Tensilica in 2013 in the business of semiconductor intellectual property core
In addition to EDA software, Cadence provides contracted methodology and design services as well as silicon design IP, and has a program aimed at making it easier for other EDA software to interoperate with the company's tools.
Conformal is a family of electronic design automation (EDA) products developed and marketed by Cadence Design Systems for Digital ASIC and Custom ASIC Design. The flagship product, Conformal-LEC belong to the class of Equivalency Checking tools that help verify Design and Netlist transformations through a formal verification proof . There are other products offered in Low Power Verification, Constraint Management, Transistor Verification and their latest offering, a product in ECO automation. Conformal-LEC was first developed by Verplex Corporation in 1998 until the company was acquired by Cadence in 2003.
Cadence was involved in a 6-year-long legal dispute with Avanti Corporation, in which Cadence claimed Avant! stole Cadence code, and Avant! denied it. According to Business Week "The Avant! case is probably the most dramatic tale of white-collar crime in the history of Silicon Valley". The Avant! executives eventually pleaded no contest and Cadence received several hundred million dollars in restitution. Avant! was then purchased by Synopsys, which paid $265 million more to settle the remaining claims. The case resulted in a number of legal precedents.
The Cadence group Quickturn was also involved in a series of legal events with Mentor Graphics/Aptix. Mentor purchased rights to an Aptix patent, then sued Cadence. In this case, the CEO of Aptix, Amr Mohsen, forged a notebook in order to make the patent case stronger. When suspicions were raised, he staged a break-in of his own car to get rid of the evidence, resulting in charges of obstruction of justice. Trying to avoid this, he attempted to flee the country, only to be caught with an illegal passport and a pile of cash. While in jail for this offense, he was recorded offering money to intimidate witnesses and kill the judge. In order to fight the new charges, he tried to feign psychological problems, but left a trail of evidence of his research into this defense, and how it might be done. He was charged with attempting to delay a federal trial by feigning incompetency, but was convicted anyway. According to the lawyers concerned, the original notebooks were not needed for the trial. The patent filing date, which was not in dispute, would have sufficed.
- May 1997: acquired Cooper & Chyan Technology, a provider of PCB and IC automatic place and router software solutions.
- December 1998: acquired Quickturn Design Systems, Inc., a market leader in microchip emulation.
- June 1999: acquired OrCAD Systems, a market leader in shrink-wrap PCB Design Tools.
- October 2002: acquired IBM's Test Design Automation group.
- September 2003: acquired Verplex Systems, a provider of Formal Verification products, Conformal Solutions and Blacktie Property Checker.
- April 6, 2004: acquired Neolinear Technology, a privately held company specializing in rapid analog design technology.
- April 7, 2005: acquired Verisity, Ltd., a provider of verification process automation solutions ($315 million in cash).
- In 2007 the company began talks with Kohlberg Kravis Roberts and Blackstone Group regarding a possible sale of the company.
- July 12, 2007: acquired Invarium, a photolithography specialist.
- August 15, 2007: acquired Clearshape, a developer of Design for Manufacturability (DFM) technology.
- March 11, 2008: acquired ChipEstimate, a developer of IC planning and IP reuse management tools.
- August 15, 2008: Cadence withdrew a $1.6 billion offer to purchase rival Mentor Graphics.
- June 17, 2010: completed acquisition of Denali Software.
- May 10, 2011: acquired Altos Design Automation, Inc., vendor of standard and complex cell libraries for the delivery of complex SoCs at advanced nodes.
- July 12, 2011: acquired Azuro, creator of clock concurrent optimization technology.
- July 2, 2012: acquired Sigrity, a leader in high-speed PCB and IC packaging analysis
- February, 2013: acquired Cosmic Circuits, a provider of analog and mixed signal intellectual property (IP) cores. Cosmic Circuits offers IP products in connectivity and mixed-signal technologies in the 40 nm and 28 nm process nodes, with 20 nm and FinFET in development. The acquisition was completed in May 2013.
- March, 2013: acquired Tensilica, known for Dataplane Processing Units (DPU). Tensilica provides configurable and extensible processors along with DPUs for audio, baseband, imaging etc. It has 200 licensees and has shipped 2 billion cores so far.
- June, 2013: completed acquisition of the IP business of Evatronix, SA SKA of Poland. This acquisition brings to Cadence IP including certified USB 2.0/3.0, MIPI, display, and storage controllers.
- February 14, 2014: acquired Forte Design Systems, a provider of high-level synthesis (HLS) software products. This includes Cynthesizer, a SystemC-based behavioral synthesis tool that enables design creation at a higher level of abstraction.
- June 16, 2014:completed acquisition of Jasper Design Automation, Inc., a market and technology leader in the fast-growing formal analysis sector.
The company has also acquired Valid Logic Systems, High Level Design (HLD), UniCAD, CadMOS, Simplex, Silicon Perspective, Plato and Get2Chip.
Denali Software, Inc. was an American software company, based in Sunnyvale, California, now acquired by Cadence. The company produces electronic design automation (EDA) software, intellectual property (IP) and design cores and platforms for memory, other standard interfaces and system-on-chip (SoC) design and verification. It has its engineering offices in Sunnyvale, Austin and Bangalore. Incorporated in 1996, Denali is headquartered in Sunnyvale, California and serves the global electronics industry with direct sales and support offices in North America, Europe, Japan and Asia.
On May 2010, Cadence Design Systems announced that it would acquire Denali for $315 million.
Valid Logic Systems
Valid Logic Systems was one of the first commercial electronic design automation (EDA) companies, now acquired by Cadence. It was founded in the early 1980s, along with Daisy Systems Corporation and Mentor Graphics, collectively known as DMV. The engineering founders were L. Curtis Widdoes, Tom McWilliams and Jeff Rubin, all of whom had worked on the S-1 supercomputer project at Livermore Labs.
Valid built both hardware and software, for schematic capture, logic simulation, static timing analysis, and packaging. Much of the initial software base derived from SCALD ("Structured Computer-Aided Logic Design"), a set of tools developed to support the design of the S-1 supercomputer at Lawrence Livermore National Laboratory. Later, Valid expanded into IC design tools and into printed circuit board layout.
At first, Valid ran schematic capture on a proprietary UNIX workstation, the SCALDSystem, with static timing analysis, simulation, and packaging running on a VAX or IBM-compatible mainframe. However, by the mid-1980s, general purpose workstations were powerful enough, significantly cheaper. Companies such as Mentor Graphics and Cadence Design Systems sold software only for such workstations. By 1990, almost all Valid software was also running on workstations, primarily those from Sun Microsystems.
- Alberto Sangiovanni-Vincentelli, co-founder.
- Richard Newton co.founder
- James Solomon, co-founder.
- Jiri Soukup, co-founder.
- Ken Kundert, fellow. Creator of the Spectre circuit simulation family of products (including SpectreRF) and the Verilog-A analog hardware description language.
- Joseph Costello, CEO, 1988–1997.
- Lip-Bu Tan, CEO, 2009–present.
- "Frequently asked questions". Cadence. Retrieved June 1, 2016.
- Design on Diagonal Path in Pursuit of a Faster Chip, John Markoff, New York Times, February 26, 2007
- Cadence Acquires Software Company, New York Times, April 11, 1990. Article describes Cadence acquiring a printed circuit design software company.
- Dylan McGrath, EE Times, "Analysis: With Fister gone, Cadence layoffs may be next". Retrieved March 3rd, 2012.
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- UNITED STATES SECURITIES AND EXCHANGE COMMISSION FORM 8-K FILING, "SEC Filing". May 13th, 2009. Retrieved March 3rd, 2012.
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- Business Week overview of the entire case, after the criminal trial but before the purchase by Synopsys.
- EEDesign article about the final settlement.
- Cadence v. Avant!: The UTSA and California Trade Secret Law, Danley, J., Berkeley Technology Law Journal, 2004, Vol 19; Part 1, pages 289-308
- Blind Spots, from IP Law and Business
- In Courts, Threats Become Alarming Fact of Life, Deborah Sontag, New York Times, 20 March 2005
- Odd legal saga takes an ugly turn, Richard Goering, EE Times, 02 August 2004
- Jury finds Mohsen guilty of perjury, obstruction of justice, Dylan McGrath, EE Times, 28 February 2006
- "Cadence Design Systems Annual Report, 1997"., page 14
- "Cadence to Acquire Quickturn Design". The New York Times. 10 December 1998. Retrieved 3 April 2015.
- "Update: Cadence gets lift from Orcad purchase". EETimes.
- Specialized Software Maker Is Said to Be in Buyout Talks, Andrew Ross Sorkin and Michael J. de la Merced, New York Times, Published: June 4, 2007
- "Cadence Withdraws Proposal to Acquire Mentor Graphics".
- "Cadence Completes Acquisition of Denali". 17 Jun 2010. Retrieved 27 May 2012.
- "Cadence Acquires Altos Design Automation".
- Former Azuro CEO Explains Clock Concurrent Optimization
- "Cadence Expands IP Portfolio with Agreement to Acquire Cosmic Circuits".
- "Cadence to Acquire Tensilica".
- Source: http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=061313_Evatronix
- Source: http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=061614_jasper
- Denali Software. "EDA / IP Solutions for SoC Design and Verification – Denali Software".
- "EE Times - Electronic Engineering Times - Connecting the Global Electronics Community". EETimes.
- Kenneth N. Gilpin; Todd S. Purdum (November 14, 1985). "BUSINESS PEOPLE; Intel Manager Becomes President of Valid Logic". New York Times. Retrieved 2013-10-17.
- Donald MacKenzie (1998). Knowing machines: essays on technical change. MIT Press. ISBN 0-262-63188-1.
- Timothy Prickett Morgan (13 April 2009). "Big-iron brains powers Schooner appliance power - Putting a ding in server size". Servers. The Register. Retrieved 2011-09-22.
- "Electronic Business". 9. Cahners. 1983: 231.
- "Business: Valid Logic to Buy Firm". San Jose Mercury News. February 6, 1987. p. 13E. Retrieved 2013-10-17.
- "Company News: Valid Logic to Buy Analog Design". New York Times. November 23, 1988. Retrieved 2013-10-17.
- "Business: Cadence to Buy Rival Valid". San Jose Mercury News. October 3, 1991. p. 1E. Retrieved 2013-10-17.
- McWilliams, T.M.; Widdoes, L.C. Jr.; Wood, L.L. (1977-09-30). "Advanced digital processor technology base development for Navy applications: the S-1 project". Lawrence Livermore National Laboratory.