Cadence Design Systems
Cadence headquarters in San Jose, CA
|Headquarters||San Jose, California, United States|
|Lip-Bu Tan, CEO; Anirudh Devgan, President|
|Revenue||$2.336 billion USD (2019)|
|$989 million USD (2019)|
Number of employees
|8,900 (October 2020)|
Cadence Design Systems, Inc., headquartered in San Jose, California, is an American multinational computational software company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Cadence Design Systems began as an electronic design automation (EDA) company, formed by the 1988 merger of Solomon Design Automation (SDA), co-founded in 1983 by Richard Newton, Alberto Sangiovanni-Vincentelli and James Solomon, and ECAD, a public company co-founded by Glen Antle and Paul Huang in 1982. SDA's CEO Joseph Costello was appointed as CEO of the newly combined company.
In 2008, Cadence's board appointed Lip-Bu Tan as acting CEO, after the resignation of Mike Fister; Tan had served on the Cadence Board of Directors since 2004. In January 2009, the Cadence's board of directors voted unanimously to confirm Lip-Bu Tan as President and CEO. Tan had been most recently CEO of Walden International, a venture capital firm, where he remains chairman of the firm.  In 2017, Cadence appointed Anirudh Devgan as president, reporting to Lip-Bu Tan.
The company develops software, hardware and intellectual properties (IP) used to design chips, systems and printed circuit boards, as well as IP covering interfaces, memory, analog, SoC peripherals, data plane processing units, and verification.
Custom IC technologies
- Virtuoso Platform. Tools for designing full-custom integrated circuits; includes schematic entry, behavioral modeling (Verilog-AMS), circuit simulation, custom layout, physical verification, extraction and back-annotation. Used mainly for analog, mixed-signal, RF, and standard-cell designs, but also memory and FPGA designs.
- Spectre X. In June 2019, Cadence introduced Spectre X parallel circuit simulator, so that users could distribute time- and frequency-domain simulations across hundreds of CPUs for faster runtime and speed.
Digital Implementation & Sign-off Technologies
- Genus, Innovus, Tempus & Voltus. In March 2020, Cadence announced that its Innovus place and route engine and optimizer were now integrated into the Genus Synthesis, with both tools using a using a common user interface and database; Additionally, machine learning capabilities were introduced to target better performance power and area across the Innovus, Tempus Timing Sign-off, and Voltus IC Power Integrity digital flow.
Other Cadence RTL to GDS II tools: Conformal Equivalence Checker, Stratus High-Level Synthesis, Joules Power Analysis, Quantus RC Extraction, Modus AutomaticTest Pattern Generation.
- Xcelium. Xcelium is a parallel simulator, introduced in 2017, based on a multi-core parallel computing architecture.
- JasperGold. JasperGold is a formal verification tool, initially introduced in 2003. In 2019, Cadence announced new machine learning technology to automate JasperGold solver selection and parameterization to achieve faster first-time proofs; additionally to optimize regression runs.
- Perspec System Verifier. Perspec was announced in 2014, for defining and verifying system-level verification scenarios, and then creating test cases to verify the scenarios using constraint-solving technology. In mid-2018, Cadence announced that Perspec supported the new Accellera Portable Test and Stimulus Standard (PSS) standard
- vManager. In 2014, Cadence announced vManager, a verification management tool for tracking verification process, including coverage, using emulation, simulation and/or formal technology as the data source(s).
- Palladium Z1. In 2015, Cadence announced the Palladium Z1 Hardware emulation platform, with over 100 million gates per hour compile speed, and greater than 1MHz execution for billion-gate designs. Cadence's Palladium emulator was originally from Cadence's Quickturn acquisition in 1998.
- Protium S1/X1. FPGA prototyping platform was officially introduced in 2014. In 2017, Cadence introduced the Protium S1 built on Xilinx Virtex UltraScale FPGAs. In 2019, Protium X1 rack-based prototyping was introduced, which Cadence claimed supported a 1.2 billion gate SoCs at around 5MHz. Palladium S1/X1 and Protium share a single compilation flow.
Design IP targeting areas including memory / storage / high-performance interface protocols (USB or PCIe controllers and PHYs), Tensilica DSP processors for audio, vision, wireless modems and convolutional neural nets. Tensilica DSP processors IP include:
PCB & Packaging technologies
- Allegro Platform. Tools for co-design of integrated circuits, packages, and PCBs, including the Specctra auto-router.
- OrCAD/PSpice. Tools for smaller design teams and individual PCB designers.
- Sigrity. Tools for signal, power integrity and thermal integrity analysis and IC package design.
- Clarity. Cadence introduced Clarity in April 2019, as part of its expansion into system analysis. Clarity is a 3D field solver for electromagnetic analysis, that uses distributed adaptive meshing to partition jobs across on hundreds of cores for gains in speed and capacity.
- Celsius. In September 2019, Cadence announced Celsius, a parallel architecture thermal solver that uses finite element analysis for solid structures and computational fluid dynamics (CFD) for fluids.
In 2020, Fortune Magazine named Cadence to Fortune's "100 Best Companies to Work For list" for the sixth consecutive year.
Also in 2020, Cadence was ranked #45 in PEOPLE magazine’s Companies that Care.
In 2019, Investor's Business Daily ranked Cadence Design Systems #5 on its 50 Best Environmental, Social, and Governance (ESG) Companies list.
In 2016, Cadence CEO Lip-Bu Tan was awarded the Dr. Morris Chang Exemplary Leadership Award by the Global Semiconductor Alliance.
|Year announced||Company||Business||Value (USD)||References|
|1989||Gateway Design Automation||Simulation software||$72 million|||
|1991||Valid Logic||Gate-level design||$198 million|| |
|1993||Comdisco Systems||Digital signal processing & communications design||$13 million|||
|1997||Cooper & Chyan Technology||Placement and routing||$422 million|| |
|1998||Quickturn Design Systems||Emulation hardware||$253 million|||
|1999||OrCAD Systems||PCB & FPGA design||$121 million|||
|2002||IBM's DFT tools & group||Design-for-Test||not disclosed|||
|2003||Celestry Design||Dense modeling, full-chip circuit simulation||not disclosed|||
|2003||Verplex||Formal verification, equivalence checkers||not disclosed|||
|2004||Neolinear||Analog & mixed-signal layout, circuit sizing||not disclosed|||
|2005||Verisity||Verification automation, hardware acceleration||$315 million|||
|2006||Praesagus||Manufacturing variation predication||$26 million|||
|2007||Invarium||Lithography-modeling and pattern-synthesis||not disclosed|||
|2007||Clear Shape||Design for Manufacturing||not disclosed|| |
|2008||Chip Estimate||IP portal, IP reuse management||not disclosed|||
|2010||Denali Software||Memory models, design IP, verification IP||$315 million|||
|2011||Altos Design Automation||Foundation IP characterization, such as memory, standard cell libraries||not disclosed|| |
|2011||Azuro||Clock concurrent optimization||not disclosed|||
|2012||Sigrity||Signal, power & thermal integrity analysis, IC package design||$80 million|| |
|2013||Cosmic Circuits||Analog & mixed-signal IP for mobile device IP, such as USB, MIPI, audio & Wi-Fi cores||not disclosed|| |
|2013||Tensilica||Dataplane processing IP||$380 million|||
|2013||Evatronix||Semiconductor IP: USB, MIPI, display, & storage interfaces||not disclosed|||
|2014||Forte Design Systems||High-level synthesis||not disclosed|||
|2014||Jasper Design Automation||Formal analysis & verification||$170 million|||
|2016||Rocketick Technologies||Multi-core parallel simulator||not disclosed|||
|2017||nusemi||High-speed Serializer/Deserializer (SerDes) communications IP||not disclosed|||
|2019||AWR Corporation||Wireless/high-frequency radio-frequency application design software||$160 million|||
|2020||Integrand Software||Method of Moments solver technology for analysis & extraction for simulating large IC and packages, characterization, and analysis in 3D-IC systems||not disclosed|||
|2020||InspectAR Augmented Interfaces||Maps electronics & labels circuit board schematics in real-time using augmented reality||not disclosed|||
The company has also acquired High-Level Design (HLD), UniCAD, CadMOS, Ambit Design Systems, Simplex, Silicon Perspective, Plato, and Get2Chip.
- In 2007, Cadence was rumored to be in talks with Kohlberg Kravis Roberts and Blackstone Group regarding a possible sale of the company.
- In 2008: Cadence withdrew a $1.6 billion offer to purchase rival Mentor Graphics.
From 1995 till 2002, Cadence was involved in a 6-year-long legal dispute with Avanti Corporation (brand name "Avant!"), in which Cadence claimed Avanti stole Cadence code, and Avanti denied it. According to Business Week "The Avanti case is probably the most dramatic tale of white-collar crime in the history of Silicon Valley". The Avanti executives eventually pleaded no contest and Cadence received several hundred million dollars in restitution. Avanti was then purchased by Synopsys, which paid $265 million more to settle the remaining claims. The case resulted in a number of legal precedents.
Quickturn Design Systems, a company acquired by Cadence, was involved in a series of legal events with Aptix Corporation. Aptix licensed a patent to Mentor Graphics and the two companies jointly sued Quickturn over an alleged patent infringement. Amr Mohsen, CEO of Aptix, forged and tampered with legal evidence and was subsequently charged with conspiracy, perjury, and obstruction of justice. Mohsen was arrested after violating his bail agreement by attempting to flee the country. While in jail, Mohsen plotted to intimidate witnesses and kill the federal judge presiding over his case. Mohsen was further charged with attempting to delay a federal trial by feigning incompetency. Due to the overwhelming misconduct, the judge ruled the lawsuit as unenforceable and Mohsen was sentenced to 17 years in prison. Mentor Graphics subsequently sued Aptix to recoup legal costs. Cadence also sued Mentor Graphics and Aptix to recover legal costs.
Berkeley Design Automation
In 2013, Cadence sued Berkeley Design Automation (BDA) for circumvention of a license scheme to link its Analog FastSpice (AFS) simulator to Cadence's Analog Design Environment (Virtuoso ADE). The lawsuit was settled less than one year later with a undisclosed payment of BDA and a multi-year agreement to support interoperability of AFS with ADE through Cadence’s official interface. BDA was bought by Mentor Graphics a few months later.
- Alberto Sangiovanni-Vincentelli, co-founder
- Richard Newton, co-founder
- James Solomon, co-founder
- Ken Kundert, fellow. Creator of the Spectre circuit simulation family of products (including SpectreRF) and the Verilog-A analog hardware description language
- Joseph Costello, CEO, 1988–1997
- Lip-Bu Tan, CEO, 2009–present
- Anirudh Devgan, President, 2017–present
- Penny Herscher
- Investor's Business Daily CEO Lip-Bu Tan Molds Troubled Cadence Into Long-Term Leader Retrieved November 12, 2020
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- "50 Best ESG Companies: A List Of Today's Top Stocks For Environmental, Social And Governance Values". Investor's Business Daily. 2 December 2019.
- GSA Website Dr. Morris Chang Exemplary Leadership Award Winner Retrieved November 28, 2020
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- UPI Cadence Design, Valid Logic Retrieved October 2, 1991
- SemiEngineering Valid Logic Systems Retrieved November 29, 2020
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- "Update: Cadence gets lift from Orcad purchase". EETimes.
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- EDN Cadence Acquires Celestry Retrieved January 16, 2003
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- Electronic Design Cadence Acquires Invarium To Beef Up DFM Technology Retrieved July 22, 2007
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- EDN Cadence to buy Denali for $315 million Retrieved May 13, 2010
- EE Times Cadence Buys Altos Design Automation Retrieved May 10, 2011
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- EE Times Cadence acquires power specialist Azuro Retrieved July 12, 2011
- Evertiq Cadence acquires Sigrity Retrieved July 3, 2012
- EE Times Cadence Pays $80 million to buy signal integrity firm Retrieved July 3, 2012
- EE News Europe Cosmic Circuits Acquisition helps Cadence to expand IP Portfolio Retrieved February 7, 2013
- EE Times Cadence buys analog IP startup Retrieved February 7, 2013
- EETimes Cadence to acquire Tensilica Retrieved March 11, 2013
- VentureBeat Cadence buys chip design firm Tensilica for $380m Retrieved March 11, 2013
- EE Times Cadence buying Evatronix to boost IP pool Retrieved May 7, 2013
- New Electronics Cadence Buys Forte, Looks to build HLS offering Retrieved February 6, 2014
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- Electronics 360 Cadence Keeps Consolidating with Jasper Purchase Retrieved April 22, 2014
- EENews Analog Cadence acquires parallel logic simulation speed-up tech with Rocketick purchase Retrieved April 13, 2016
- eeNews Analog Cadence grows high-speed communications IP offering with nusemi dea Retrieved November 2, 2017
- Silicon Valley Business Journal Cadence Design Systems to acquire AWR Corp. from National Instruments for $160M Retrieved December 2, 2019
- New Electronics Cadence makes Integrand acquisition Retrieved February 17, 2020
- everythingRF Cadence Accelerates Innovation in 5G RF Communications by Acquiring Integrand Retrieved February 14, 2020
- CBC A new chapter: Silicon Valley firm buys St. John's tech company Retrieved August 13, 2020
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- Business Week (pay wall) overview of the entire case, after the criminal trial but before the purchase by Synopsys.
- EEDesign article about the final settlement.
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- In Courts, Threats Become Alarming Fact of Life, Deborah Sontag, The New York Times, 20 March 2005
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- Jury finds Mohsen guilty of perjury, obstruction of justice, Dylan McGrath, EE Times, 28 February 2006
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