Cadence Design Systems
|Headquarters||San Jose, California, United States|
|Lip-Bu Tan, CEO |
Anirudh Devgan, President
|Revenue||US$2.682 Billion (Fiscal Year Ended January 2, 2021)|
|US$0.645 Billion (Fiscal Year Ended January 2, 2021)|
|US$0.590 Billion (Fiscal Year Ended January 2, 2021)|
|Total assets||US$3.950 Billion (Fiscal Year Ended January 2, 2021)|
|Total equity||US$2.493 Billion (Fiscal Year Ended January 2, 2021)|
Number of employees
|8,900 (October 2020)|
Cadence Design Systems, Inc. (stylized as cādence), headquartered in San Jose, California, is an American multinational computational software company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Cadence Design Systems began as an electronic design automation (EDA) company, formed by the 1988 merger of Solomon Design Automation (SDA), co-founded in 1983 by Richard Newton, Alberto Sangiovanni-Vincentelli and James Solomon, and ECAD, a public company co-founded by Ping Chao, Glen Antle and Paul Huang in 1982. SDA's CEO Joseph Costello was appointed as CEO of the newly combined company.
In 2008, Cadence's board appointed Lip-Bu Tan as acting CEO, after the resignation of Mike Fister; Tan had served on the Cadence Board of Directors since 2004. In January 2009, the Cadence's board of directors voted unanimously to confirm Lip-Bu Tan as President and CEO. Tan had been most recently CEO of Walden International, a venture capital firm, where he remains chairman of the firm.
In July 2021, Cadence stated Anirudh Devgan will assume the role of president and CEO and Lip-Bu Tan will become executive chairman on December 15, 2021. Devgan joined Cadence in 2012 and was appointed president in 2017.
The company develops software, hardware and intellectual properties (IP) used to design chips, systems and printed circuit boards, as well as IP covering interfaces, memory, analog, SoC peripherals, data plane processing units, and verification.
Custom IC technologies
- Virtuoso Platform. Tools for designing full-custom integrated circuits; includes schematic entry, behavioral modeling (Verilog-AMS), circuit simulation, custom layout, physical verification, extraction and back-annotation. Used mainly for analog, mixed-signal, RF, and standard-cell designs, but also memory and FPGA designs.
- Spectre X. In June 2019, Cadence introduced Spectre X parallel circuit simulator, so that users could distribute time- and frequency-domain simulations across hundreds of CPUs for faster runtime and speed.
- AWR is a radio frequency to millimeter wave design environment for designing 5G/wireless products. Used for communications, aerospace and defense, semiconductor, computer and consumer electronics.
Digital Implementation & Sign-off Technologies
- Genus, Innovus, Tempus & Voltus. In March 2020, Cadence announced that its Innovus place and route engine and optimizer were now integrated into Genus Synthesis, with both tools using a common user interface and database.
- Stratus High-level synthesis tool that creates RTL implementations from C, C++, or SystemC code.
- Cerebrus. In July 2021, Cadence announced its machine learning-based Cerebrus chip explorer product to automatically optimize the Cadence digital design flow for specified power, performance, and area goals across multiple blocks. Cerebrus utilizes a reinforcement learning approach to increase efficiency each time the optimization process is repeated.
Other Cadence RTL to GDS II tools: Conformal Equivalence Checker, Stratus High-Level Synthesis, Joules Power Analysis, Quantus RC Extraction, Modus AutomaticTest Pattern Generation.
- Xcelium. Xcelium is a parallel simulator, introduced in 2017, based on a multi-core parallel computing architecture.
- JasperGold. JasperGold is a formal verification tool, initially introduced in 2003. In 2019, Cadence announced new machine learning technology to automate JasperGold solver selection and parameterization to achieve faster first-time proofs; additionally to optimize regression runs.
- Perspec System Verifier. Perspec was announced in 2014, for defining and verifying system-level verification scenarios, and then creating test cases to verify the scenarios using constraint-solving technology. In mid-2018, Cadence announced that Perspec supported the new Accellera Portable Test and Stimulus Standard (PSS) standard
- vManager. vManager is verification management tool for tracking verification process, including coverage, using emulation, simulation and/or formal technology as the data source(s).
- Palladium. In 2015, Cadence announced the Palladium Z1 Hardware emulation platform, with over 100 million gates per hour compile speed, and greater than 1 MHz execution for billion-gate designs. Cadence's Palladium emulator was originally from Cadence's Quickturn acquisition in 1998. In 2021, Cadence announced Palladium Z2, claiming a 1.5X performance and 2X capacity improvement over the prior Palladium Z1, for more than 18 billion gate+ capacity. Additionally, Cadence claimed Palladium Z2 could compile 10 billion gates in under 10 hours.
- Protium. The Protium FPGA prototyping platform was officially introduced in 2014. In 2017, Cadence introduced the Protium S1 built on Xilinx Virtex UltraScale FPGAs. In 2019, Protium X1 rack-based prototyping was introduced, which Cadence claimed supported a 1.2 billion gate SoCs at around 5 MHz. Palladium S1/X1 and Protium share a single compilation flow. In 2021, Protium X2 was announced; Cadence claimed a 1.5X performance and 2X capacity improvement over Protium X1, and that Protium X2 could compile 10 billion gates in under 24 hours.
Design IP targeting areas including memory / storage / high-performance interface protocols (USB or PCIe controllers and PHYs), Tensilica DSP processors for audio, vision, wireless modems and convolutional neural nets. Tensilica DSP processors IP include:
Tensilica Vision DSPs for Imaging, Vision and AI processing; Tensilica HiFi DSPs for Audio/Voice/Speech processing; Tensilica Fusion DSPs for IoT; Tensilica ConnX DSPs for Radar, Lidar, and Communications processing.; and Tensilica DNA Processor Family for AI acceleration
In 2021, Cadence launched the Tensilica AI Platform to accelerate AI SoC development and improve power, performance and area -- targeting mobile, IoT, automotive, intelligent sensor, and industrial AI SoC designs.
PCB & Packaging technologies
- Allegro Platform. Tools for co-design of integrated circuits, packages, and PCBs, including the Specctra auto-router.
- OrCAD/PSpice. Tools for smaller design teams and individual PCB designers.
- OrbitIO Interconnect Designer. Die/package planning & route optimization tool.
- InspectAR. InspectAR uses augmented reality to map out complicated circuit board electronics for real-time labelling of board schematics.
- Sigrity. Tools for signal, power integrity and thermal integrity analysis and IC package design.
- Clarity. Cadence introduced Clarity in April 2019, as part of its expansion into system analysis. Clarity is a 3D field solver for electromagnetic analysis, that uses distributed adaptive meshing to partition jobs across on hundreds of cores for gains in speed and capacity.
- Celsius. In September 2019, Cadence announced Celsius, a parallel architecture thermal solver that uses finite element analysis for solid structures and computational fluid dynamics (CFD) for fluids.
- Omnis. Omnis is a computational fluid dynamics, mesh generation, multi-physics simulation & optimization product, with established applications in aerospace, automotive, industrial and marine. (From NUMECA acquisition in 2021.)
- Pointwise. Pointwise computational fluid dynamics (CFD) mesh generation. (From Pointwise acquisition in 2021.)
In 2020, Fortune Magazine named Cadence to Fortune's "100 Best Companies to Work For list" for the sixth consecutive year.
Also in 2020, Cadence was ranked #45 in PEOPLE magazine’s Companies that Care.
In 2019, Investor's Business Daily ranked Cadence Design Systems #5 on its 50 Best Environmental, Social, and Governance (ESG) Companies list.
In 2016, Cadence CEO Lip-Bu Tan was awarded the Dr. Morris Chang Exemplary Leadership Award by the Global Semiconductor Alliance.
|Year announced||Company||Business||Value (USD)||References|
|1989||Gateway Design Automation||Simulation software||$72 million|||
|1991||Valid Logic||Gate-level design||$198 million|||
|1993||Comdisco Systems||Digital signal processing & communications design||$13 million|||
|1997||Cooper & Chyan Technology||Placement and routing||$422 million|||
|1998||Bell Labs Design Automation||Simulation and verification software||$45 million|||
|1998||Quickturn Design Systems||Emulation hardware||$253 million|||
|1999||OrCAD Systems||PCB & FPGA design||$121 million|||
|2002||IBM's DFT tools & group||Design-for-Test||not disclosed|||
|2003||Celestry Design||Dense modeling, full-chip circuit simulation||not disclosed|||
|2003||Verplex||Formal verification, equivalence checkers||not disclosed|||
|2004||Neolinear||Analog & mixed-signal layout, circuit sizing||not disclosed|||
|2005||Verisity||Verification automation, hardware acceleration||$315 million|||
|2006||Praesagus||Manufacturing variation predication||$26 million|||
|2007||Invarium||Lithography-modeling and pattern-synthesis||not disclosed|||
|2007||Clear Shape||Design for Manufacturing||not disclosed|||
|2008||Chip Estimate||IP portal, IP reuse management||not disclosed|||
|2010||Denali Software||Memory models, design IP, verification IP||$315 million|||
|2011||Altos Design Automation||Foundation IP characterization, such as memory, standard cell libraries||not disclosed|||
|2011||Azuro||Clock concurrent optimization||not disclosed|||
|2012||Sigrity||Signal, power & thermal integrity analysis, IC package design||$80 million|||
|2013||Cosmic Circuits||Analog & mixed-signal IP for mobile device IP, such as USB, MIPI, audio & Wi-Fi cores||not disclosed|||
|2013||Tensilica||Dataplane processing IP||$380 million|||
|2013||Evatronix||Semiconductor IP: USB, MIPI, display, & storage interfaces||not disclosed|||
|2014||Forte Design Systems||High-level synthesis||not disclosed|||
|2014||Jasper Design Automation||Formal analysis & verification||$170 million|||
|2016||Rocketick Technologies||Multi-core parallel simulator||not disclosed|||
|2017||nusemi||High-speed Serializer/Deserializer (SerDes) communications IP||not disclosed|||
|2019||AWR Corporation||Wireless/high-frequency radio-frequency application design software||$160 million|||
|2020||Integrand Software||Method of moments solver technology for analysis & extraction for simulating large IC and packages, characterization, and analysis in 3D-IC systems||not disclosed|||
|2020||InspectAR Augmented Interfaces||Maps electronics & labels circuit board schematics in real-time using augmented reality||not disclosed|||
|2021||NUMECA||CFD, mesh generation, multi-physics simulation & optimization||not disclosed|||
|2021||Pointwise||Computational fluid dynamics (CFD) mesh generation||not disclosed|||
The company has also acquired High-Level Design (HLD), UniCAD, CadMOS, Ambit Design Systems, Simplex, Silicon Perspective, Plato, and Get2Chip.
- In 2007, Cadence was rumored to be in talks with Kohlberg Kravis Roberts and Blackstone Group regarding a possible sale of the company.
- In 2008, Cadence withdrew a $1.6 billion offer to purchase rival Mentor Graphics.
From 1995 till 2002, Cadence was involved in a 6-year-long legal dispute with Avanti Corporation (brand name "Avant!"), in which Cadence claimed Avanti stole Cadence code, and Avanti denied it. According to Business Week "The Avanti case is probably the most dramatic tale of white-collar crime in the history of Silicon Valley". The Avanti executives eventually pleaded no contest and Cadence received several hundred million dollars in restitution. Avanti was then purchased by Synopsys, which paid $265 million more to settle the remaining claims. The case resulted in a number of legal precedents.
Quickturn Design Systems, a company acquired by Cadence, was involved in a series of legal events with Aptix Corporation. Aptix licensed a patent to Mentor Graphics and the two companies jointly sued Quickturn over an alleged patent infringement. Amr Mohsen, CEO of Aptix, forged and tampered with legal evidence and was subsequently charged with conspiracy, perjury, and obstruction of justice. Mohsen was arrested after violating his bail agreement by attempting to flee the country. While in jail, Mohsen plotted to intimidate witnesses and kill the federal judge presiding over his case. Mohsen was further charged with attempting to delay a federal trial by feigning incompetency. Due to the overwhelming misconduct, the judge ruled the lawsuit as unenforceable and Mohsen was sentenced to 17 years in prison. Mentor Graphics subsequently sued Aptix to recoup legal costs. Cadence also sued Mentor Graphics and Aptix to recover legal costs.
Berkeley Design Automation
In 2013, Cadence sued Berkeley Design Automation (BDA) for circumvention of a license scheme to link its Analog FastSpice (AFS) simulator to Cadence's Analog Design Environment (Virtuoso ADE). The lawsuit was settled less than one year later with an undisclosed payment of BDA and a multi-year agreement to support interoperability of AFS with ADE through Cadence’s official interface. BDA was bought by Mentor Graphics a few months later.
- Alberto Sangiovanni-Vincentelli, co-founder
- Richard Newton, co-founder
- James Solomon, co-founder
- Ken Kundert, fellow. Creator of the Spectre circuit simulation family of products (including SpectreRF) and the Verilog-A analog hardware description language
- Ray Bingham, CEO 1999-?
- Michael Fister, CEO ?-2009
- Joseph Costello, CEO, 1988–1997
- Lip-Bu Tan, CEO, 2009–present
- Anirudh Devgan, President, 2017–present
- Penny Herscher
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