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The CAMIF, also the Camera Interface block is the hardware block that interfaces with different image sensor interfaces and provides a standard output that can be used for subsequent image processing.
The camera interface's parallel interface consists of the following lines :-
8 to 12 bits parallel data line
- These are parallel data lines that carry pixel data. The data transmitted on these lines change with every Pixel Clock (PCLK).
Horizontal Sync (HSYNC)
- This is a special signal that goes from the camera sensor or ISP to the camera interface. An HSYNC indicates that one line of the frame is transmitted.
Vertical Sync (VSYNC)
- This signal is transmitted after the entire frame is transferred. This signal is often a way to indicate that one entire frame is transmitted.
Pixel Clock (PCLK)
- This is the pixel clock and it would change on every pixel.
NOTE: The above lines are all treated as input lines to the Camera Interface hardware.
Let us suppose that a sensor is transmitting a VGA frame 640x480. The video frame is of a format RGB888. Let's assume that we have a camera sensor transmitting 8 bits per pixel clock (PCLK). This means to transfer one pixel of data, 3 PCLKs would be required. The HSYNC would be fired by the sensor after every 640 x 3, 1920 PCLKs. A VSYNC would be fired by the sensor after the entire frame is transmitted i.e. after 1920x480, 921600 PCLKs.
The camera interface's hardware block (that could be a part of any SOC) would constantly monitor the above lines to see if the sensor has transmitted anything. A typical camera interface would come with some internal buffering and would also have an associated DMA to transfer the image to the destination memory. The buffer would capture the incoming pixels to temporarily buffer them, and using the DMA the pixels would be transferred (probably line by line) through multiple burst DMA transfers to a destination address in the memory (pre programmed by the camera interface driver programmer). The camera interface's programmer interface might also give a facility of issuing hardware interrupts upon the receipt of the HSYNC, VSYNC signals to the host micro-controller. This could serve as a useful trigger for DMA reprogramming if required.
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