Catapult C

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Catapult C Synthesis, a commercial electronic design automation product of Calypto Design Systems, is a high-level synthesis tool, sometimes called algorithmic synthesis or ESL synthesis. Catapult C takes ANSI C/C++ and SystemC inputs[1] and generates register transfer level (RTL) code targeted to FPGAs and ASICs.[2]


In 2004, Mentor Graphics formally announced its Catapult C high level synthesis product offering hierarchical design support for synthesizing pipelined, multi-block subsystems from untimed ANSI C/C++ descriptions. Catapult C's main functionality was generating RTL (VHDL and Verilog) targeted to ASICs and FPGAs. Users specified constraints for timing and area, and provided a clock period and destination technology. Mentor also announced a Catapult C Library Builder for ASIC Designers to collect detailed characterization data.[3]

In 2005, Mentor announced extensions to Catapult C to automatically create SystemC transaction-level models and wrappers, for simulation of the design in verification environments supporting SystemC. Mentor also introduced interface synthesis to map the data transfer implied by passing of C++ function arguments to hardware interfaces such as wires, registers, handshaked registers, memories, buses or more complex user-defined interfaces.[4]

In 2006, Mentor announced Catapult SL (System Level) for automatically creating signal processing subsystems. Catapult SL could coordinate the partitioning of sequential C operations into multiple blocks within the subsystem, including partitioning into multiple clock domains. Catapult SL automatically inserts appropriate inter-block channels and memory buffers to assemble the sub-system.[5]

In January 2009, Mentor announced an integration between Catapult C and its Vista SystemC design and simulation environment to automatically generate transaction-level models (TLM). In this process, the untimed ANSI C++ input to Catapult is encapsulated in a TLM wrapper; timing information is extracted from the synthesis results and back-annotated in the resulting model. The flow is compatible with the TLM-2.0 standard from the Open SystemC Initiative (OSCI).[6]

In June 2009, Mentor announced that it enhanced Catapult C with the ability to synthesize control logic, create power-optimized RTL netlists, with automatic multi-level clock gating, and an automated verification flow to enable a debug of the RTL against the original C++ input.[7]

In January 2010, Mentor announced the ability for Catapult C to take direct SystemC input, including both cycle-based and transaction level (TLM) support.[8]

In May 2011, Mentor announced that Catapult C supported TLM synthesis. Abstract TLM models are converted to pin-accurate, protocol-specific, SystemC models, and from there, synthesized to RTL code. Existing synthesizable descriptions can be converted to TLMs.[9]

In August 2011, Catapult C was acquired by Calypto Design Systems.[10]


CatapultC synthesizes ANSI C/C++ without proprietary extensions. The C/C++ language support includes pointers, classes, templates, template specialization and operator overloading, which facilitate design reuse methodology over RTL code.[11]

Catapult C supports both algorithmic and control logic synthesis.[12]

Designers do iterations with CatC to pick their preferred micro architecture for specified performance and area constraints.[13] Catapult has a graphic user interface with a visual view of the hardware circuit it is scheduling, as well as the clock reference between the C code and the Verilog RTL code. Catapult C has 3 types of simulation using the original C/C++ testbench: Cycle-based, RTL-based, and Gate-Level based.[14]

Catapult C supports SystemC model generation intended for virtual platforms, and a SystemC test environment to verify the generated RTL against the original C++ using the original C++ testbench.

Catapult C supports the synthesis of Transaction Level Models (TLM), including standard off-the-shelf bus interfaces and custom protocols.[15]

Competing HLS Products[edit]


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