Clock recovery

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Some digital data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive) are sent without an accompanying clock signal. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a phase-locked loop (PLL). This process is commonly known as clock and data recovery (CDR). It is very closely related to the problem of carrier recovery, which is the process of re-creating a phase-locked version of the carrier when a suppressed carrier modulation scheme is used. These problems were first addressed in a 1956 paper, which introduced a clock recovery method now known as the Costas loop.[1] Since then many additional methods have been developed.

In order for this scheme to work, a data stream must transition frequently enough to correct for any drift in the PLL's oscillator. The limit for how long a clock recovery unit can operate without a transition is known as its maximum consecutive identical digits (CID) specification. To ensure frequent transitions, some sort of self-clocking signal is used, often a run length limited encoding; 8b/10b encoding is very common, while Manchester encoding serves the same purpose in old revisions of 802.3 local area networks.

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  1. ^ Costas, J.P. (1956). "Synchronous communications". Proceedings of the IRE. IEEE. 44 (12): 1713–1718. doi:10.1109/JRPROC.1956.275063.