Clock recovery

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Some digital data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive and serial communication networks such as Ethernet) are sent without an accompanying clock signal. The receiver generates a clock from an approximate frequency reference, and then phase-aligns the clock to the transitions in the data stream with a phase-locked loop (PLL). This is one method of performing a process commonly known as clock and data recovery (CDR). Other methods include the use of a delay-locked loop and oversampling of the data stream.[1] Oversampling can be done blind using multiple phases of a free-running clock to create multiple samples of the input and then selecting the best sample. Or, a counter can be used that is driven by a sampling clock running at some multiple of the data stream frequency, with the counter reset on every transition of the data stream and the data stream sampled at some predetermined count. These two types of oversampling are sometimes called spatial and time respectively.[2] The best bit error ratio (BER) is obtained when the samples are taken as far away as possible from any data stream transitions.[3] While most oversampling designs using a counter employ a sampling clock frequency that is an even multiple of the data stream, an odd multiple is better able to create a sampling point further from any data stream transitions and can do so at nearly half the frequency of a design using an even multiple. In oversampling type CDRs, the signal used to sample the data can be used as the recovered clock.

Clock recovery is very closely related to the problem of carrier recovery, which is the process of re-creating a phase-locked version of the carrier when a suppressed carrier modulation scheme is used. These problems were first addressed in a 1956 paper, which introduced a clock recovery method now known as the Costas loop.[4] Since then many additional methods have been developed.

In order for this scheme to work, a data stream must transition frequently enough to correct for any drift in the PLL's oscillator. The limit for how long a clock recovery unit can operate without a transition is known as its maximum consecutive identical digits (CID) specification. To ensure frequent transitions, some sort of self-clocking signal is used, often a run length limited encoding; 8b/10b encoding is very common, while Manchester encoding serves the same purpose in old revisions of 802.3 local area networks.

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  1. ^ Hsieh, Ming-ta; Sobelman, Gerald (December 2008). "Architectures for Multi-Gigabit Wire-Linked Clock and Data Recovery". IEEE Circuits and Systems Magazine. Institute of Electrical and Electronics Engineers. 8 (4): 45–57. doi:10.1109/MCAS.2008.930152. 
  2. ^ Bi, Zhuo; Wang, Zhen; Xu, Meihua (2012). "Mini SerDes Based on Economic FPGA" (PDF). International Proceedings of Computer Science and Information Technology. Singapore: IACSIT Press. 51: 337–338. doi:10.7763/IPCSIT.2012.V51.57. Retrieved 2016-09-07. 
  3. ^ admin (Aug 2015). "Beginners Guide To Clock Data Recovery". Arrow Devices. Retrieved 2016-09-07. 
  4. ^ Costas, J.P. (1956). "Synchronous communications". Proceedings of the IRE. IEEE. 44 (12): 1713–1718. doi:10.1109/JRPROC.1956.275063.