Comparison of ARMv8-A cores

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This is a table of 64/32-bit ARMv8-A architecture cores, comparing microarchitectures which implement the AArch64 instruction set and mandatory or optional extensions of it. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7 and NEON (SIMD) chips. Some of these chips have coprocessors, such as the AppliedMicro Helix that also includes cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.

Table[edit]

Company Core Released Revision Decode Pipeline
depth
Out-of-order
execution
Branch
prediction
big.LITTLE role Execution
ports
Fab
(in nm)
L1 cache
Instr + Data
(in KiB)
L2 cache L3 cache Core
configu-
rations
DMIPS/
MHz
ARM Holdings Cortex-A32 (32-bit)[1] ARMv8-A
(32-bit)
? LITTLE 28[2] 8–32 + 8–32 0–1 MiB No 1-4+
Cortex-A35[3] ARMv8-A 2-wide[4] 8 No Yes LITTLE ? 28 / 16 / 14 8–64 + 8–64 0 / 128 KiB–1 MiB No 1–4+ 1.78
Cortex-A53[5] ARMv8-A 2-wide 8 No Conditional+
Indirect branch
prediction
big/LITTLE 2 28 / 20 / 16 / 14 8–64 + 8–64 128 KiB–2 MiB No 1–4+ 2.24
Cortex-A55[6] ARMv8.2-A 2-wide 8 No big/LITTLE 2 28 / 20 / 16 / 14/ 10 16–64 + 16–64 0–256 KiB/core 0–4 MiB 1–8+ ?
Cortex-A57 ARMv8-A 3-wide 15 Yes
3-wide dispatch
Two-level big 8 28 / 20 / 16[7] / 14 48 + 32 0.5–2 MiB No 1–4+ 4.6
Cortex-A72[8] ARMv8-A 3-wide 15 Yes
5-wide dispatch
Two-level big 8 28 / 16 48 + 32 0.5–4 MiB No 1–4+ 4.72
Cortex-A73[9] ARMv8-A 2-wide 11–12 Yes
6-wide dispatch
Two-level big 7 28 / 16 / 10 64 + 32/64 1–8 MiB No 1–4+ ~6.35
Cortex-A75[10] ARMv8.2-A 3-wide 11–13 Yes
9-wide dispatch
Two-level big 8 28 / 16 / 10 64 + 64 256–512 KiB/core 0–4 MiB 1–8+ ?
Apple Inc. Cyclone[11] ARMv8-A 6-wide[12] 16[12] Yes[12] ? No 9[12] 28[13] 64 + 64[12] 1 MiB[12] 4 MiB[12] 2[14] ?
Typhoon ? 6-wide[15] 16[15] Yes[15] ? No 20 64 + 64[12] 1 MiB[15] 4 MiB[12] 2, 3 (A8X) ?
Twister ? 6-wide[15] 16[15] Yes[15] ? No 16 / 14 64 + 64[15] 3 MiB[15] 4 MiB[15] 2 ?
Hurricane ? 6-wide 16 Yes ? "big" (in Apple A10 paired with "LITTLE" Zephyr
cores e.g. Apple's own similar implementation)
16 64 + 64[16] 3 MiB[16] 4 MiB[16] 2 +
Zephyr
?
Nvidia Denver[17][18] ? 2-wide hardware
decoder, up to
7-wide variable-
length VLIW
micro-ops
13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.
Direct+
Indirect branch
prediction
No 7 28 128 + 64 2 MiB No 2 ?
Denver 2[19] ? ? 13 ? ? "Super" Nvidia's own implementation ? 16 128+64 2 MiB No 2 ?
Cavium ThunderX[20][21] ARMv8-A 2-wide ? No Two-level ? 28 78 + 32[22][23] 16 MiB[22][23] No 8–16, 24–48 ?
ThunderX2[21]
(ex. Broadcom Vulcan[24])
ARMv8.1-A
[25]
8-wide
"4 μops"[26][27]
"quad-threaded"
? Yes[28] Multi-level ? ? 16[29] 32 + 32
(data 8-way)
32 MiB shared[30] ? 54 ?
AppliedMicro Helix ? ? ? ? ? ? ? ? 40 / 28 32 + 32 (per core;
write-through
w/parity)[31]
256 KiB shared
per core pair (with ECC)
1 MiB/core 2, 4, 8 ?
X-Gene ? 4-wide 15 Yes ? ? ? 40[32] 8 MiB 8 4.2
X-Gene 2 ? 4-wide 15 Yes ? ? ? 28[33] 8 MiB 8 4.2
X-Gene 3[33] ? ? ? ? ? ? ? 16 ? ? 32 MiB 32 ?
Qualcomm Kryo ARMv8-A ? ? Yes Two-level? "big" or "LITTLE"
Qualcomm's own similar implementation
? 14[34] / 10 32 + 32[35] 0,5–1 MiB (SD820/821)
2 MiB (SD835, high cluster)
No 2, 4 6.3
Falkor[36] 2016-12-07 ARMv8-A ? ? ? ? ? ? 10 ? ? yes 48 ?
Samsung Mongoose[37][38] ARMv8-A 4-wide 15–17 Yes
4-wide dispatch[39]
Two-level big 8 14 / 10 64 + 32 2 MiB[40] no 4 ?
Company Core Released Revision Decode Pipeline
depth
Out-of-order
execution
Branch
prediction
big.LITTLE role Execution
ports
Fab
(in nm)
L1 cache
Instr + Data
(in KiB)
L2 cache L3 cache Core
configu-
rations
DMIPS/
MHz

As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

See also[edit]

References[edit]

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  3. ^ "Cortex-A35 Processor". ARM. ARM Ltd. 
  4. ^ http://anandtech.com/show/9769/arm-announces-cortex-a35
  5. ^ "Cortex-A53 Processor". ARM. ARM Ltd. 
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  14. ^ Lal Shimpi, Anand (17 September 2013). "The iPhone 5s Review: A7 SoC Explained". AnandTech. Retrieved 3 July 2014. 
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  16. ^ a b c "Apple A10 Fusion". system-on-a-chip.specout.com. Retrieved 2016-10-01. 
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  18. ^ Gwennap, Linley. "Denver Uses Dynamic Translation to Outperform Mobile Rivals". The Linley Group. Retrieved 24 April 2015. 
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  24. ^ https://reviews.llvm.org/D30510
  25. ^ https://reviews.llvm.org/D21500
  26. ^ https://hpcuserforum.com/presentations/santafe2014/Broadcom%20Monday%20night.pdf
  27. ^ http://www.linleygroup.com/events/agenda.php?num=24&day=1
  28. ^ http://www.cavium.com/ThunderX2_ARM_Processors.html
  29. ^ "Broadcom Announces Server-Class ARMv8-A Multi-Core Processor Architecture". Broadcom. 15 October 2013. Retrieved 11 August 2014. 
  30. ^ http://www.cnx-software.com/2016/06/01/cavium-introduces-54-cores-64-bit-armv8-thunderx2-soc-for-servers-with-100gbe-sata-3-pcie-gen3-interfaces/
  31. ^ Ganesh T S (3 October 2014). "ARMv8 Goes Embedded with Applied Micro's HeliX SoCs". AnandTech. Retrieved 9 October 2014. 
  32. ^ Morgan, Timothy Prickett (12 August 2014). "Applied Micro Plots Out X-Gene ARM Server Future". Enterprisetech. Retrieved 9 October 2014. 
  33. ^ a b De Gelas, Johan (15 March 2017). "AppliedMicro's X-Gene 3 SoC Begins Sampling". Anandtech. Retrieved 15 March 2017. 
  34. ^ "Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute". Qualcomm. 2 September 2015. Retrieved 6 September 2015. 
  35. ^ http://www.anandtech.com/show/9837/snapdragon-820-preview/
  36. ^ Shilov, Anton (16 December 2016). "Qualcomm Demos 48-Core Centriq 2400 SoC in Action, Begins Sampling". Anandtech. Retrieved 8 March 2017. 
  37. ^ http://www.anandtech.com/show/9781/samsung-announces-exynos-8890-with-cat1213-modem-and-custom-cpu
  38. ^ http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed
  39. ^ Frumusanu, Andrei. "Hot Chips 2016: Exynos M1 Architecture Disclosed". Anandtech. Retrieved 29 Many 2017.  Check date values in: |access-date= (help)
  40. ^ http://www.theregister.co.uk/2016/08/22/samsung_m1_core/