Comparison of ARMv8-A cores

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This is a table of 64/32-bit ARMv8-A architecture cores comparing microarchitectures which implement the AArch64 instruction set and mandatory or optional extensions of it. Most chips support 32-bit AArch32 for legacy applications. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7 and NEON (SIMD) chips. Some of these chips have coprocessors also include cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.

Table[edit]

Company Core Released Revision Decode Pipeline
depth
Out-of-order
execution
Branch
prediction
big.LITTLE role Exec.
ports
Fab
(in nm)
Simult. MT L0 cache L1 cache
Instr + Data
(in KiB)
L2 cache L3 cache Core
configu-
rations
DMIPS/
MHz
ARM part number (in the main ID register)
ARM Holdings Cortex-A32 (32-bit)[1] 2017 ARMv8.0-A
(only 32-bit)
2-wide 8 No LITTLE ? 28[2] No No 8–64 + 8–64 0–1 MiB No 1-4+ 0xD01
Cortex-A34 (64-bit)[3] 2019 ARMv8.0-A
(only 64-bit)
2-wide 8 No LITTLE ? No No 8–64 + 8–64 0–1 MiB No 1-4+ 0xD02
Cortex-A35[4] 2017 ARMv8.0-A 2-wide[5] 8 No Yes LITTLE ? 28 / 16 /
14 / 10
No No 8–64 + 8–64 0 / 128 KiB–1 MiB No 1–4+ 1.78 0xD04
Cortex-A53[6] 2014 ARMv8.0-A 2-wide 8 No Conditional+
Indirect branch
prediction
big/LITTLE 2 28 / 20 /
16 / 14 / 10
No No 8–64 + 8–64 128 KiB–2 MiB No 1–4+ 2.24 0xD03
Cortex-A55[7] 2017 ARMv8.2-A 2-wide 8 No big/LITTLE 2 28 / 20 /
16 / 14 / 12 / 10
No No 16–64 + 16–64 0–256 KiB/core 0–4 MiB 1–8+ 2.65[8] 0xD05
Cortex-A57[9] 2013 ARMv8.0-A 3-wide 15 Yes
3-wide dispatch
Two-level big 8 28 / 20 /
16[10] / 14
No No 48 + 32 0.5–2 MiB No 1–4+ 4.6 0xD07
Cortex-A65[11] 2019 ARMv8.2-A ? ? Yes Two-level ? 2 ? No No ? ? ? ? ? 0xD06
Cortex-A65AE[12] 2019 ARMv8.2-A ? ? Yes Two-level ? 2 ? SMT2 No 16-64 + 16-64 64-256 KiB 0-4 MB 1–8 ? 0xD43
Cortex-A72[13] 2015 ARMv8.0-A 3-wide 15 Yes
5-wide dispatch
Two-level big 8 28 / 16 No No 48 + 32 0.5–4 MiB No 1–4+ 4.72 0xD08
Cortex-A73[14] 2016 ARMv8.0-A 2-wide 11–12 Yes
4-wide dispatch
Two-level big 7 28 / 16 / 10 No No 64 + 32/64 1–8 MiB No 1–4+ ~6.35 0xD09
Cortex-A75[7] 2017 ARMv8.2-A 3-wide 11–13 Yes
6-wide dispatch
Two-level big 8? 28 / 16 / 10 No No 64 + 64 256–512 KiB/core 0–4 MiB 1–8+ 8.2-9.5[15] 0xD0A
Cortex-A76[16] 2018 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch
Two-level big 8 10 / 7 No No 64 + 64 256–512 KiB/core 1–4 MiB 1–4 10.7-12.4[17] 0xD0B
Cortex-A76AE[18] 2018 ARMv8.2-A ? ? Yes Two-level big ? ? SMT2 No ? ? ? ? ? 0xD0E
Cortex-A77[19] 2019 ARMv8.2-A 4-wide 11–13 Yes
10-wide dispatch
Two-level big 12 7 No 1.5K entries 64 + 64 256–512 KiB/core 1–4 MiB 1-4 ? 0xD0D
Cortex-A78[20][21] 2020 ARMv8.2-A 4-wide Yes Yes big 13 No 1.5K entries 32/64 + 32/64 256–512 KiB/core 1–4 MiB 1-4 ? 0xD41
Cortex-X1[22] 2020 ARMv8.2-A 5-wide[22] ? Yes Yes big 15 No 3K entries 64 + 64 up to 1 MiB[22] up to 8 MiB[22] custom[22] ? 0xD44
Apple Inc. Cyclone[23] 2013 ARMv8.0-A 6-wide[24] 16[24] Yes[24] Yes No 9[24] 28[25] No No 64 + 64[24] 1 MiB[24] 4 MiB[24] 2[26] ?
Typhoon 2014 ARMv8.0‑A 6-wide[27] 16[27] Yes[27] Yes No 9 20 No No 64 + 64[24] 1 MiB[27] 4 MiB[24] 2, 3 (A8X) ?
Twister 2015 ARMv8.0‑A 6-wide[27] 16[27] Yes[27] Yes No 9 16 / 14 No No 64 + 64[27] 3 MiB[27] 4 MiB[27]
No (A9X)
2 ?
Hurricane 2016 ARMv8.1‑A 6-wide[28] 16 Yes Yes "big" (In A10/A10X paired with "LITTLE" Zephyr
cores)
9 16 (A10)
10 (A10X)
No No 64 + 64[29] 3 MiB[29] (A10)
8 MiB (A10X)
4 MiB[29] (A10)
No (A10X)
2x Hurricane + 2x Zephyr (A10)
3x Hurricane + 3x Zephyr (A10X)
?
Zephyr 2016 ARMv8.1‑A 3-wide 12 Yes Yes LITTLE 5 16 (A10)
10 (A10X)
No No 32 + 32[30] 1 MiB 4 MiB[29] (A10)
No (A10X)
2x Hurricane + 2x Zephyr (A10)
3x Hurricane + 3x Zephyr (A10X)
?
Monsoon 2017 ARMv8.2‑A[31] 7-wide 16 Yes Yes "big" (In Apple A11 paired with "LITTLE" Mistral
cores)
13 10 No No 64 + 64[30] 8 MiB No 2x Monsoon + 4× Mistral ?
Mistral 2017 ARMv8.2‑A[31] 3-wide 12 Yes Yes LITTLE 5 10 No No 32 + 32[30] 1 MiB No 2x Monsoon + 4× Mistral ?
Vortex 2018 ARMv8.3‑A[32] 7-wide 16 Yes Yes "big" (In Apple A12/Apple A12X/Apple A12Z paired with "LITTLE" Tempest
cores)
13 7 No No 128 + 128[30] 8 MiB No 2x Vortex + 4x Tempest (A12)
4x Vortex + 4x Tempest (A12X/A12Z)
?
Tempest 2018 ARMv8.3‑A[32] 3-wide 12 Yes Yes LITTLE 5 7 No No 32 + 32[30] 2 MiB No 2x Vortex + 4x Tempest (A12)
4x Vortex + 4x Tempest (A12X/A12Z)
?
Lightning 2019 ARMv8.4‑A [33] 7-wide 16 Yes Yes "big" (In Apple A13 paired with "LITTLE" Thunder
cores)
13 7 No No 128 + 128[34] 8 MiB No 2x Lightning + 4x Thunder ?
Thunder 2019 ARMv8.4‑A [35] 3-wide 12 Yes Yes LITTLE 5 7 No No 32 + 48[36] 4 MiB No 2x Lightning + 4x Thunder ?
Nvidia Denver[37][38] 2014 ARMv8‑A 2-wide hardware
decoder, up to
7-wide variable-
length VLIW
micro-ops
13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.
Direct+
Indirect branch
prediction
No 7 28 No No 128 + 64 2 MiB No 2 ?
Denver 2[39] 2016 ARMv8‑A ? 13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.
Direct+
Indirect branch
prediction
"Super" Nvidia's own implementation ? 16 No No 128 + 64 2 MiB No 2 ?
Carmel 2018 ARMv8.2‑A ? Direct+
Indirect branch
prediction
? 12 No No 128 + 64 2 MiB (4 MiB @ 8 cores) 2 (+ 8) ?
Cavium ThunderX[40][41] 2014 ARMv8-A 2-wide 9[41] Yes[40] Two-level ? 28 No No 78 + 32[42][43] 16 MiB[42][43] No 8–16, 24–48 ?
ThunderX2
[44](ex. Broadcom Vulcan[45])
2018[46] ARMv8.1-A
[47]
4-wide
"4 μops"[48][49]
? Yes[50] Multi-level ? ? 16[51] SMT4 No 32 + 32
(data 8-way)
256 KiB
per core[52]
1 MiB
per core[52]
16-32[52] ?
Marvell ThunderX3 2020[53] ARMv8.3+[53] 8-wide ? Yes
4-wide dispatch
Multi-level ? 7 7[53] SMT4[53] ? 64 + 32 512 KiB
per core
90 MiB 60 ?
Applied

Micro

Helix 2014 ? ? ? ? ? ? ? 40 / 28 No No 32 + 32 (per core;
write-through
w/parity)[54]
256 KiB shared
per core pair (with ECC)
1 MiB/core 2, 4, 8 ?
X-Gene 2013 ? 4-wide 15 Yes ? ? ? 40[55] No No 8 MiB 8 4.2
X-Gene 2 2015 ? 4-wide 15 Yes ? ? ? 28[56] No No 8 MiB 8 4.2
X-Gene 3[56] 2017 ? ? ? ? ? ? ? 16 No No ? ? 32 MiB 32 ?
Qualcomm Kryo 2016 ARMv8-A ? ? Yes Two-level? "big" or "LITTLE"
Qualcomm's own similar implementation
? 14[57] No No 32+24[58] 0.5–1 MiB 2, 4 6.3
Kryo 2XX 2017 ARMv8-A 2-wide 11–12 Yes
7-wide dispatch
Two-level big 7 14 / 11 / 10 [59] No No 64 + 32/64? 512 KiB/Gold Core No 4 ?
2-wide 8 No Conditional+
Indirect branch
prediction
? 2 No No 8–64? + 8–64? 256 KiB/Silver Core 4 ?
Kryo 3XX 2018 ARMv8.2-A 3-wide 11–13 Yes
8-wide dispatch
Two-level big 8 10[59] No No 64+64[59] 256 KiB/Gold Core 2 MiB 4 ?
2-wide 8 No Conditional+
Indirect branch
prediction
? 28 No No 16–64? + 16–64? 128 KiB/Silver 4 ?
Kryo 4XX 2019 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch
Yes big 8 11 / 8 / 7 No No 64 + 64 512 KiB/Gold Prime

256 KiB/Gold

2 MiB 1+3 ?
2-wide 8 No Conditional+
Indirect branch
prediction
? 2 No No 16–64? + 16–64? 128 KiB/Silver 4 ?
Falkor[60][61] 2017[62] "ARMv8.1-A features";[61] AArch64 only (not 32-bit)[61] 4-wide 10–15 Yes
8-wide dispatch
Yes ? 8 10 No 24 KiB 88[61] + 32 500KiB 1.25MiB 40-48 ?
Samsung M1/M2[63][64] 2015 ARMv8-A 4-wide 13[65] Yes
9-wide dispatch[66]
Two-level big 8 14 / 10 No No 64 + 32 2 MiB[67] no 4 ?
M3[65][68] 2018 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch
Two-level big 12 10 No No 64 + 64 512 KiB per core 4096KB 4 ?
M4[69] 2019 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch
Two-level big 12 8 / 7 No No 64 + 64 512 KiB per core 4096KB 2 ?
Fujitsu A64FX[70][71] 2019 ARMv8.2-A 4/2-wide 7+ Yes
5-way?
Yes n/a 8+ 7 No No 64 + 64 8MiB per 12+1 cores No 48+4 1.9GHz+; 15GF/W+.
HiSilicon TaiShan V110[72] 2019 ARMv8.2-A 4-wide ? Yes Yes n/a 8 7 No No 64 + 64 512 KiB per core 1 MiB per core ? ?
Company Core Released Revision Decode Pipeline
depth
Out-of-order
execution
Branch
prediction
big.LITTLE role Exec.
ports
Fab
(in nm)
Simult. MT L0 cache L1 cache
Instr + Data
(in KiB)
L2 cache L3 cache Core
configu-
rations
DMIPS/
MHz
ARM part number (in the main ID register)

As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

See also[edit]

References[edit]

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