Comparison of instruction set architectures
Computer architectures are often described as n-bit architectures. Today n is often 8, 16, 32, or 64, but other sizes have been used. This is actually a strong simplification. A computer architecture often has a few more or less "natural" datasizes in the instruction set, but the hardware implementation of these may be very different. Many architectures have instructions operating on half and/or twice the size of respective processors major internal datapaths. Examples of this are the 8080, Z80, MC68000 as well as many others. On this type of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The external databus width is often not useful to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses. The NS32764 had a 64-bit bus, but used 32-bit registers.
The width of addresses may or may not be different from the width of data. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.
The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture will allow
A := B + C
to be computed in one instruction.
A two-operand architecture will allow
A := A + B
to be computed in one instruction, so two instructions will need to be executed to simulate a single three-operand instruction
A := B A := A + C
An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big endian architectures instead order them with the most significant byte at the lowest-numbered address. The x86 and the ARM architectures as well as several 8-bit architectures are little endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big endian, but many (including ARM) are now configurable.
Usually the number of registers is a power of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" of register files of architectures, mostly to simplify indexing modes. This table only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program pointer (PC). Those are not counted unless mentioned. Note that some architectures, such as SPARC, have register windows; for those architectures, the count below indicates how many registers are available within a register window. Also, non-architected registers for register renaming are not counted.
Note, a common type of architecture, "load-store", is a synonym for "Register Register" below, meaning no instructions access memory except special – load to register(s) – and store from register(s) – with the possible exceptions of atomic memory operations for locking.
The table below compares basic information about instruction sets to be implemented in the CPU architectures:
|Instruction set||Bits||Version||Introduced||Max # operands||Type||Design||Registers (excluding FP/vector)||Instruction encoding||Branch evaluation||Endianness||Extensions||Open||Royalty free|
|Alpha||64||1992||3||Register Register||RISC||32 (including "zero")||Fixed (32-bit)||Condition register||Bi||, , ,||No||Unknown|
|ARM||32/16||ARMv7 and earlier||1983||3||Register Register||RISC||
||Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2: Variable (16- and 32-bit)||Condition code||Bi||NEON, Jazelle, , TrustZone, LPAE||Unknown||No|
|ARMv8-A||64/32||ARMv8-A||2011||3||Register Register||RISC||31||Fixed (32-bit). In ARMv7 compatibility mode: Thumb: Fixed (16-bit), Thumb-2: Variable (16- and 32-bit), A64||Condition code||Bi||None (all extensions of ARMv7 are non-optional)||Unknown||No|
|AVR||8||1997||2||Register Register||RISC||32 (16 on "reduced architecture")||Variable (mostly 16-bit, four instructions are 32-bit)||Condition register, skip conditioned on an I/O or general purpose register bit, compare and skip||Little||Unknown||Unknown|
|AVR32||32||Rev 2||2006||2–3||RISC||15||Variable||Big||Java Virtual Machine||Unknown||Unknown|
||Variable (64- or 128-bit)||Condition code||Little|
|eSi-RISC||16/32||2009||3||Register Register||RISC||8–72||Variable (16- or 32-bit)||Compare and branch and condition register||Bi||User-defined instructions||No||No|
|Itanium (IA-64)||64||2001||Register Register||EPIC||128||Condition register||Bi (selectable)||Intel Virtualization Technology||No||No|
|M32R||32||1997||RISC||16||Fixed (16- or 32-bit)||Bi||Unknown||Unknown|
|Motorola 68k||32||1979||2||Register Memory||CISC||8 data and 8 address||Variable||Condition register||Big||Unknown||Unknown|
|Mico32||32||2006||3||Register Register||RISC||32||Fixed (32-bit)||Compare and branch||Big||User-defined instructions||Yes||Yes|
|MIPS||64 (32→64)||5||1981||1–3||Register Register||RISC||4–32 (including "zero")||Fixed (32-bit)||Condition register||Bi||MDMX, MIPS-3D||Unknown||No|
|MMIX||64||1999||3||Register Register||RISC||256||Fixed (32-bit)||Big||Yes||Yes|
|6502||8||1975||1||Register Memory||CISC||1||Variable (8- to 32-bit)||Condition register||Little|
|65k||64 (8→64)||2006?||1||Memory Memory||CISC||1||Variable (8-bit to 256 bytes)||Compare and branch||Little|
|8051||32 (8→32)||1977?||1||Register Register||CISC||
||Variable (8-bit to 128 bytes)||Compare and branch||Little|
|NS320xx||32||1982||5||Memory Memory||CISC||8||Variable Huffman coded, up to 23 bytes long||Condition code||Little||BitBlt instructions||Unknown||Unknown|
|OpenRISC||32, 64||2010||3||Register Register||RISC||16 or 32||Fixed||Yes||Yes|
|PA-RISC (HP/PA)||64 (32→64)||2.0||1986||3||Register Register||RISC||32||Fixed (32-bit)||Compare and branch||Big → Bi||Multimedia Acceleration eXtensions (MAX), MAX-2||No||Unknown|
|PowerPC||32/64 (32→64)||2.07||1991||3||Register Register||RISC||32||Fixed (32-bit), Variable||Condition code||Big/Bi||AltiVec, APU, VSX, Cell||Yes||No|
|Rx||64/32/16||2000||3||Memory Memory||CISC||4 integer + 4 address||Variable||Compare and branch||Little||Unknown||No|
|RISC-V||32, 64, 128||2010||Register Register||RISC||32 (including "zero")||Variable||Compare and branch||Little||Yes||Yes|
|SPARC||64 (32→64)||OSA2015||1985||3||Register Register||RISC||32 (including "zero")||Fixed (32-bit)||Condition code||Big → Bi||VIS 1.0, 2.0, 3.0, 4.0||Yes||Yes|
|SuperH (SH)||32||1990s||2||Register Register / Register Memory||RISC||16||Fixed (16- or 32-bit), Variable||Condition code (single bit)||Bi||Unknown||Unknown|
|System/360 / System/370 / z/Architecture||64 (32→64)||3||1964||Register Memory / Memory Memory||CISC||16||Variable||Condition code||Big||Unknown||Unknown|
|Transputer||32 (4→64)||1987||1||Stack machine||MISC||0||Variable (8 ~ 120 bytes)||Compare and branch||Little|
|VAX||32||1977||6||Memory Memory||CISC||16||Variable||Compare and branch||Little||VAX Vector Architecture||Unknown||Unknown|
|x86||16, 32, 64 (16→32→64)||1978||2 (integer)
3 (AVX-512 only)
||Variable||Condition code||Little||x87, IA-32, MMX, 3DNow!, SSE, SSE2, PAE, x86-64, SSE3, SSE4, SSE5, AVX, AES, FMA||No||No|
|Z80||8||1976||2||Register Memory||CISC||8||Variable (8 to 32 bits)||Condition register||Little|
|Architecture||Bits||Version||Introduced||Max # operands||Type||Design||Registers (excluding FP/vector)||Instruction encoding||Branch evaluation||Endianness||Extensions||Open||Royalty free|
- Central processing unit (CPU)
- CPU design
- Comparison of CPU microarchitectures
- Instruction set
- List of instruction sets
- Benchmark (computing)
- ARMv8 Technology Preview
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- http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-processor-2516655.html Oracle SPARC Processor Documentation
- http://sparc.org/technical-documents/#ArchLic SPARC Architecture License