Compute Express Link

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Compute Express Link
Year created2019; 0 years ago (2019)
Speed1.x (32 GT/s):
  • 3.938 GB/s (×1)
  • 63.01 GB/s (×16)
Websitewww.computeexpresslink.org

Compute Express Link (CXL) is an open standard interconnect for high-speed CPU-to-device and CPU-to-memory designed to accelerate next-generation data center performance. [1] CXL is built upon the PCI Express (PCIe) physical and electrical interface with protocols in three key areas: I/O, memory and cache coherence.

History[edit]

CXL Specification 1.0[edit]

On March 11, 2019, the CXL Specification 1.0 based upon PCIe 5.0 was released. The founding promoter members of the CXL specification included: Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, Intel and Microsoft.[2]

CXL Specification 1.1[edit]

In June, 2019, the CXL Specification 1.1 was released.

On July 18, 2019, AMD joined CXL.[3]

Compute Express Link Consortium Members[edit]

Founding promoters as of September 21, 2019, are:

Current members as of September 21, 2019, are:

Implementations[edit]

On April 2, 2019 Intel announced their family of Agilex FPGAs featuring CXL.[4]

Also see[edit]

References[edit]

  1. ^ "ABOUT CXL". Compute Express Link. Retrieved 2019-08-09.
  2. ^ Cutress, Ian. "CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel". www.anandtech.com. Retrieved 2019-08-09.
  3. ^ "AMD Joins Consortia to Advance CXL, a New High-... | Community". community.amd.com. Retrieved 2019-08-09.
  4. ^ "How do the new Intel Agilex FPGA family and the CXL coherent interconnect fabric intersect?". PSG@Intel. 2019-05-03. Retrieved 2019-08-09.

External links[edit]