Compute Express Link

From Wikipedia, the free encyclopedia
Jump to navigation Jump to search
Compute Express Link
Year created2019; 1 year ago (2019)
Speed1.x (32 GT/s):
  • 3.938 GB/s (×1)
  • 63.01 GB/s (×16)

Compute Express Link (CXL) is an open standard interconnection for high-speed central processing unit (CPU)-to-device and CPU-to-memory, designed to accelerate next-generation data center performance.[1][2][3][4] CXL is built on the PCI Express (PCIe) physical and electrical interface with protocols in three key areas: input/output (I/O), memory, and cache coherence.

On April 2, 2020, the Compute Express Link and Gen-Z Consortiums have announced their execution of a memorandum of understanding (MoU), describing a mutual plan for collaboration between the two organizations.[5][6]


CXL Specification 1.0[edit]

On March 11, 2019, the CXL Specification 1.0 based on PCIe 5.0 was released. The founding promoter members of the CXL specification included: Alibaba Group, Cisco Systems, Dell EMC, Facebook, Google, Hewlett Packard Enterprise (HPE), Huawei, Intel, and Microsoft.[7]

CXL Specification 1.1[edit]

In June, 2019, the CXL Specification 1.1 was released.

On July 18, 2019, Advanced Micro Devices (AMD) joined CXL.[8]

CXL Specification 2.0[edit]

In November 10, 2020, the CXL Specification 2.0 was released.

Consortium members[edit]

Founding members[9] as of September 21, 2019, are:

Current members[10] as of September 21, 2019, are:


On April 2, 2019, Intel announced their family of Agilex FPGAs featuring CXL.[11]

See also[edit]


  1. ^ "ABOUT CXL". Compute Express Link. Retrieved 2019-08-09.
  2. ^ "Synopsys Delivers Industry's First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs". Yahoo! Finance. Retrieved 2019-11-09.
  3. ^ "A Milestone in Moving Data". Intel Newsroom. Intel. Retrieved 2019-11-09.
  4. ^ "Compute Express Link Consortium (CXL) Officially Incorporates; Announces Expanded Board of Directors". Business Wire. 2019-09-17. Retrieved 2019-11-09.
  5. ^ "CXL Consortium and Gen-Z Consortium Announce MOU Agreement" (PDF). Beaverton, Oregon. April 2, 2020. Retrieved September 25, 2020.
  6. ^ "CXL Consortium and Gen-Z Consortium Announce MOU Agreement". April 2, 2020. Retrieved April 11, 2020.
  7. ^ Cutress, Ian. "CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel". Anandtech. Retrieved 2019-08-09.
  8. ^ Papermaster, Mark (July 18, 2019). "AMD Joins Consortia to Advance CXL, a New High-Speed Interconnect for Breakthrough Performance". Community.AMD. Retrieved 2020-09-25.
  9. ^ "Compute Express Link: Our Members". CXL Consortium. 2020. Retrieved 2020-09-25.
  10. ^
  11. ^ "How do the new Intel Agilex FPGA family and the CXL coherent interconnect fabric intersect?". PSG@Intel. 2019-05-03. Retrieved 2019-08-09.

External links[edit]