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A parallel computing platform and programming model
Developer(s) Nvidia Corporation
Initial release June 23, 2007; 9 years ago (2007-06-23)
Stable release
7.5 / September 8, 2015; 12 months ago (2015-09-08)
Operating system Windows XP and later,
Mac OS X, Linux
Platform Supported GPUs
License Freeware

CUDA is a parallel computing platform and application programming interface (API) model created by Nvidia.[1] It allows software developers and software engineers to use a CUDA-enabled graphics processing unit (GPU) for general purpose processing – an approach termed GPGPU. The CUDA platform is a software layer that gives direct access to the GPU's virtual instruction set and parallel computational elements, for the execution of compute kernels.[2]

The CUDA platform is designed to work with programming languages such as C, C++, and Fortran. This accessibility makes it easier for specialists in parallel programming to use GPU resources, in contrast to prior APIs like Direct3D and OpenGL, which required advanced skills in graphics programming. Also, CUDA supports programming frameworks such as OpenACC and OpenCL.[2] When it was first introduced by Nvidia, the name CUDA was an acronym for Compute Unified Device Architecture,[3] but Nvidia subsequently dropped the use of the acronym.


Further information: Graphics processing unit

The graphics processing unit (GPU), as a specialized computer processor, addresses the demands of real-time high-resolution 3D graphics compute-intensive tasks. By 2012, GPUs had evolved into highly parallel multi-core systems allowing very efficient manipulation of large blocks of data. This design is more effective than general-purpose central processing unit (CPUs) for algorithms in situations where processing large blocks of data is done in parallel, such as:

Programming abilities[edit]

Example of CUDA processing flow
1. Copy data from main mem to GPU mem
2. CPU instructs the process to GPU
3. GPU execute parallel in each core
4. Copy the result from GPU mem to main mem

The CUDA platform is accessible to software developers through CUDA-accelerated libraries, compiler directives such as OpenACC, and extensions to industry-standard programming languages including C, C++ and Fortran. C/C++ programmers use 'CUDA C/C++', compiled with nvcc, Nvidia's LLVM-based C/C++ compiler.[4] Fortran programmers can use 'CUDA Fortran', compiled with the PGI CUDA Fortran compiler from The Portland Group.

In addition to libraries, compiler directives, CUDA C/C++ and CUDA Fortran, the CUDA platform supports other computational interfaces, including the Khronos Group's OpenCL,[5] Microsoft's DirectCompute, OpenGL Compute Shaders and C++ AMP.[6] Third party wrappers are also available for Python, Perl, Fortran, Java, Ruby, Lua, Haskell, R, MATLAB, IDL, and native support in Mathematica.

In the computer game industry, GPUs are used for graphics rendering, and for game physics calculations (physical effects such as debris, smoke, fire, fluids); examples include PhysX and Bullet. CUDA has also been used to accelerate non-graphical applications in computational biology, cryptography and other fields by an order of magnitude or more.[7][8][9][10][11]

CUDA provides both a low level API and a higher level API. The initial CUDA SDK was made public on 15 February 2007, for Microsoft Windows and Linux. Mac OS X support was later added in version 2.0,[12] which supersedes the beta released February 14, 2008.[13] CUDA works with all Nvidia GPUs from the G8x series onwards, including GeForce, Quadro and the Tesla line. CUDA is compatible with most standard operating systems. Nvidia states that programs developed for the G8x series will also work without modification on all future Nvidia video cards, due to binary compatibility.[citation needed]


CUDA has several advantages over traditional general-purpose computation on GPUs (GPGPU) using graphics APIs:

  • Scattered reads – code can read from arbitrary addresses in memory
  • Unified virtual memory (CUDA 4.0 and above)
  • Unified memory (CUDA 6.0 and above)
  • Shared memory – CUDA exposes a fast shared memory region that can be shared among threads. This can be used as a user-managed cache, enabling higher bandwidth than is possible using texture lookups.[14]
  • Faster downloads and readbacks to and from the GPU
  • Full support for integer and bitwise operations, including integer texture lookups


  • CUDA does not support the full C standard, as it runs host code through a C++ compiler, which makes some valid C (but invalid C++) code fail to compile.[15][16]
  • Interoperability with rendering languages such as OpenGL is one-way, with OpenGL having access to registered CUDA memory but CUDA not having access to OpenGL memory.
  • Copying between host and device memory may incur a performance hit due to system bus bandwidth and latency (this can be partly alleviated with asynchronous memory transfers, handled by the GPU's DMA engine)
  • Threads should be running in groups of at least 32 for best performance, with total number of threads numbering in the thousands. Branches in the program code do not affect performance significantly, provided that each of 32 threads takes the same execution path; the SIMD execution model becomes a significant limitation for any inherently divergent task (e.g. traversing a space partitioning data structure during ray tracing).
  • Unlike OpenCL, CUDA-enabled GPUs are only available from Nvidia.[17]
  • No emulator or fallback functionality is available for modern revisions.
  • Valid C/C++ may sometimes be flagged and prevent compilation due to optimization techniques the compiler is required to employ to use limited resources.[citation needed]
  • A single process must run spread across multiple disjoint memory spaces, unlike other C language runtime environments.
  • C++ run-time type information (RTTI) is unsupported in CUDA code, due to lack of support in the underlying hardware.
  • Exception handling is unsupported in CUDA code due to performance overhead that would be incurred with many thousands of parallel threads running.
  • CUDA (with compute ability 2.x) allows a subset of C++ class functionality, for example member functions may not be virtual (this restriction will be removed in some future release). [See CUDA C Programming Guide 3.1 – Appendix D.6]
  • In single precision on first generation CUDA compute ability 1.x devices, denormal numbers are unsupported and are instead flushed to zero, and the precisions of the division and square root operations are slightly lower than IEEE 754-compliant single precision math. Devices that support compute ability 2.0 and above support denormal numbers, and the division and square root operations are IEEE 754 compliant by default. However, users can obtain the prior faster gaming-grade math of compute ability 1.x devices if desired by setting compiler flags to disable accurate divisions and accurate square roots, and enable flushing denormal numbers to zero.[18]

GPUs supported[edit]

Supported CUDA Level of GPU and Card. See direct also Nvidia:

GPUs GeForce Quadro Tesla Tegra
1.0 Tesla G80 GeForce 8800 Ultra, GeForce 8800 GTX, GeForce 8800 GTS(G80) Quadro FX 5600, Quadro FX 4600, Quadro Plex 2100 S4 Tesla C870, Tesla D870, Tesla S870
1.1 G92, G94, G96, G98, G84, G86 GeForce GTS 250, GeForce 9800 GX2, GeForce 9800 GTX, GeForce 9800 GT, GeForce 8800 GTS(G92), GeForce 8800 GT, GeForce 9600 GT, GeForce 9500 GT, GeForce 9400 GT, GeForce 8600 GTS, GeForce 8600 GT, GeForce 8500 GT, GeForce G110M, GeForce 9300M GS, GeForce 9200M GS, GeForce 9100M G, GeForce 8400M GT, GeForce G105M Quadro FX 4700 X2, Quadro FX 3700, Quadro FX 1800, Quadro FX 1700, Quadro FX 580, Quadro FX 570, Quadro FX 470, Quadro FX 380, Quadro FX 370, Quadro FX 370 Low Profile, Quadro NVS 450, Quadro NVS 420, Quadro NVS 290, Quadro NVS 295, Quadro Plex 2100 D4, Quadro FX 3800M, Quadro FX 3700M, Quadro FX 3600M, Quadro FX 2800M, Quadro FX 2700M, Quadro FX 1700M, Quadro FX 1600M, Quadro FX 770M, Quadro FX 570M, Quadro FX 370M, Quadro FX 360M, Quadro NVS 320M, Quadro NVS 160M, Quadro NVS 150M, Quadro NVS 140M, Quadro NVS 135M, Quadro NVS 130M, Quadro NVS 450, Quadro NVS 420, Quadro NVS 295
1.2 GT218, GT216, GT215 GeForce GT 340*, GeForce GT 330*, GeForce GT 320*, GeForce 315*, GeForce 310*, GeForce GT 240, GeForce GT 220, GeForce 210, GeForce GTS 360M, GeForce GTS 350M, GeForce GT 335M, GeForce GT 330M, GeForce GT 325M, GeForce GT 240M, GeForce G210M, GeForce 310M, GeForce 305M Quadro FX 380 Low Profile, Nvidia NVS 300, Quadro FX 1800M, Quadro FX 880M, Quadro FX 380M, Nvidia NVS 300, NVS 5100M, NVS 3100M, NVS 2100M, ION
1.3 GT200, GT200b GeForce GTX 295, GTX 285, GTX 280, GeForce GTX 275, GeForce GTX 260 Quadro FX 5800, Quadro FX 4800, Quadro FX 4800 for Mac, Quadro FX 3800, Quadro CX, Quadro Plex 2200 D2 Tesla C1060, Tesla S1070, Tesla M1060
2.0 Fermi GF100, GF110 GeForce GTX 590, GeForce GTX 580, GeForce GTX 570, GeForce GTX 480, GeForce GTX 470, GeForce GTX 465, GeForce GTX 480M Quadro 6000, Quadro 5000, Quadro 4000, Quadro 4000 for Mac, Quadro Plex 7000, Quadro 5010M, Quadro 5000M Tesla C2075, Tesla C2050/C2070, Tesla M2050/M2070/M2075/M2090
2.1 GF104, GF106 GF108, GF114, GF116, GF117, GF119 GeForce GTX 560 Ti, GeForce GTX 550 Ti, GeForce GTX 460, GeForce GTS 450, GeForce GTS 450*, GeForce GT 640 (GDDR3), GeForce GT 630, GeForce GT 620, GeForce GT 610, GeForce GT 520, GeForce GT 440, GeForce GT 440*, GeForce GT 430, GeForce GT 430*, GeForce GT 420*, GeForce GTX 675M, GeForce GTX 670M, GeForce GT 635M, GeForce GT 630M, GeForce GT 625M, GeForce GT 720M, GeForce GT 620M, GeForce 710M, GeForce 610M, GeForce 820M, GeForce GTX 580M, GeForce GTX 570M, GeForce GTX 560M, GeForce GT 555M, GeForce GT 550M, GeForce GT 540M, GeForce GT 525M, GeForce GT 520MX, GeForce GT 520M, GeForce GTX 485M, GeForce GTX 470M, GeForce GTX 460M, GeForce GT 445M, GeForce GT 435M, GeForce GT 420M, GeForce GT 415M, GeForce 710M, GeForce 410M Quadro 2000, Quadro 2000D, Quadro 600, Quadro 410, Quadro 4000M, Quadro 3000M, Quadro 2000M, Quadro 1000M, NVS 5400M, NVS 5200M, NVS 4200M
3.0 Kepler GK104, GK106, GK107 GeForce GTX 770, GeForce GTX 760, GeForce GT 740, GeForce GTX 690, GeForce GTX 680, GeForce GTX 670, GeForce GTX 660 Ti, GeForce GTX 660, GeForce GTX 650 Ti BOOST, GeForce GTX 650 Ti, GeForce GTX 650, GeForce GTX 880M, GeForce GTX 780M, GeForce GTX 770M, GeForce GTX 765M, GeForce GTX 760M, GeForce GTX 680MX, GeForce GTX 680M, GeForce GTX 675MX, GeForce GTX 670MX, GeForce GTX 660M, GeForce GT 750M, GeForce GT 650M, GeForce GT 745M, GeForce GT 645M, GeForce GT 740M, GeForce GT 730M, GeForce GT 640M, GeForce GT 640M LE, GeForce GT 735M, GeForce GT 730M Quadro K5000, Quadro K4200, Quadro K4000, Quadro K2000, Quadro K2000D, Quadro K600, Quadro K420, Quadro K500M, Quadro K510M, Quadro K610M, Quadro K1000M, Quadro K2000M, Quadro K1100M, Quadro K2100M, Quadro K3000M, Quadro K3100M, Quadro K4000M, Quadro K5000M, Quadro K4100M, Quadro K5100M Tesla K10, GRID K340, GRID K520
3.2 GK20A Tegra K1
3.5 GK110, GK208 GeForce GTX Titan Z, GeForce GTX Titan Black, GeForce GTX Titan, GeForce GTX 780 Ti, GeForce GTX 780, GeForce GT 640 (GDDR5), GeForce GT 630 v2, GeForce GT 730, GeForce GT 720, GeForce GT 710,GeForce GT 740M (64-bit, DDR3) Quadro K6000, Quadro K5200 Tesla K40, Tesla K20x, Tesla K20
3.7 GK210 Tesla K80
5.0 Maxwell GM107, GM108 GeForce GTX 750 Ti, GeForce GTX 750, GeForce GTX 960M, GeForce GTX 950M, GeForce 940M, GeForce 930M, GeForce GTX 860M, GeForce GTX 850M, GeForce 845M, GeForce 840M, GeForce 830M Quadro K2200, Quadro K1200, Quadro K620, Quadro M2000M, Quadro M1000M, Quadro M600M, Quadro K620M
5.2 GM200, GM204, GM206 GeForce GTX Titan X, GeForce GTX 980 Ti, GeForce GTX 980, GeForce GTX 970, GeForce GTX 960, GeForce GTX 950, GeForce GTX 750 SE, GeForce GTX 980M, GeForce GTX 970M, GeForce GTX 965M Quadro M6000 24GB, Quadro M6000, Quadro M5000, Quadro M4000, Quadro M2000, Quadro M5500, Quadro M5000M, Quadro M4000M, Quadro M3000M Tesla M4, Tesla M40, Tesla M6, Tesla M60
5.3 GM20B Tegra X1
6.0 Pascal GP100 Tesla P100
6.1 GP102, GP104, GP106 Nvidia Titan X, GeForce GTX 1080, GTX 1070, GTX 1060 Quadro P6000, Quadro P5000
7.0 Volta

'*' - OEM-only products

Version features and specifications[edit]

Feature support (unlisted features are
supported for all compute abilities)
Compute ability (version)
1.0 1.1 1.2 1.3 2.x 3.0 3.5 3.7 5.0 5.2 6.0 6.1
Integer atomic functions operating on
32-bit words in global memory
No Yes
atomicExch() operating on 32-bit floating
point values in global memory
Integer atomic functions operating on
32-bit words in shared memory
No Yes
atomicExch() operating on 32-bit floating
point values in shared memory
Integer atomic functions operating on
64-bit words in global memory
Warp vote functions
Double-precision floating-point operations No Yes
Atomic functions operating on 64-bit
integer values in shared memory
No Yes
Floating-point atomic addition operating on
32-bit words in global and shared memory
_syncthreads_count(), _syncthreads_and(),
Surface functions
3D grid of thread block
Warp shuffle functions No Yes
Funnel shift No Yes
Dynamic parallelism
Technical specifications Compute ability (version)
1.0 1.1 1.2 1.3 2.x 3.0 3.5 3.7 5.0 5.2 5.3 6.0 6.1
Maximum dimensionality of grid of thread blocks 2 3
Maximum x-dimension of a grid of thread blocks 65535 231 − 1
Maximum y-, or z-dimension of a grid of thread blocks 65535
Maximum dimensionality of thread block 3
Maximum x- or y-dimension of a block 512 1024
Maximum z-dimension of a block 64
Maximum number of threads per block 512 1024
Warp size 32
Maximum number of resident blocks per multiprocessor 8 16 32
Maximum number of resident warps per multiprocessor 24 32 48 64
Maximum number of resident threads per multiprocessor 768 1024 1536 2048
Number of 32-bit registers per multiprocessor 8 K 16 K 32 K 64 K 128 K 64 K
Maximum number of 32-bit registers per thread block N/A 32 K 64 K 32 K
Maximum number of 32-bit registers per thread 124 63 255
Maximum amount of shared memory per multiprocessor 16 KB 48 KB 112 KB 64 KB 96 KB 64 KB
Number of shared memory banks 16 32
Amount of local memory per thread 16 KB 512 KB
Constant memory size 64 KB
Cache working set per multiprocessor for constant memory 8 KB 10 KB
Cache working set per multiprocessor for texture memory 6 – 8 KB 12 KB 12 – 48 KB 24 KB 48 KB N/A 24 KB
Maximum width for 1D texture reference bound to a CUDA
8192 65536
Maximum width for 1D texture reference bound to linear
Maximum width and number of layers for a 1D layered
texture reference
8192 × 512 16384 × 2048
Maximum width and height for 2D texture reference bound
to a CUDA array
65536 × 32768 655362
Maximum width and height for 2D texture reference bound
to a linear memory
Maximum width and height for 2D texture reference bound
to a CUDA array supporting texture gather
N/A 163842
Maximum width, height, and number of layers for a 2D
layered texture reference
8192 × 8192 × 512 16384 × 16384 × 2048
Maximum width, height and depth for a 3D texture
reference bound to linear memory or a CUDA array
20483 40963
Maximum width and number of layers for a cubemap
layered texture reference
N/A 16384 × 2046
Maximum number of textures that can be bound to a
128 256
Maximum width for a 1D surface reference bound to a
CUDA array
Maximum width and number of layers for a 1D layered
surface reference
65536 × 2048
Maximum width and height for a 2D surface reference
bound to a CUDA array
65536 × 32768
Maximum width, height, and number of layers for a 2D
layered surface reference
65536 × 32768 × 2048
Maximum width, height, and depth for a 3D surface
reference bound to a CUDA array
65536 × 32768 × 2048
Maximum width and number of layers for a cubemap
layered surface reference
32768 × 2046
Maximum number of surfaces that can be bound to a
8 16
Maximum number of instructions per kernel 2 million 512 million
Architecture specifications Compute ability (version)
1.0 1.1 1.2 1.3 2.0 2.1 3.0 3.5 3.7 5.0 5.2 6.0 6.1
Number of ALU lanes for integer and single-precision floating-point arithmetic operations 8[19] 32 48 192 128 64 128
Number of special function units for single-precision floating-point transcendental functions 2 4 8 32 16 32
Number of texture filtering units for every texture address unit or render output unit (ROP) 2 4 8 16 8
Number of warp schedulers 1 2 4 2 4
Number of instructions issued at once by scheduler 1 2[20]

For more information please visit this site: and read Nvidia CUDA programming guide.[21]


This example code in C++ loads a texture from an image into an array on the GPU:

texture<float, 2, cudaReadModeElementType> tex;

void foo()
  cudaArray* cu_array;

  // Allocate array
  cudaChannelFormatDesc description = cudaCreateChannelDesc<float>();
  cudaMallocArray(&cu_array, &description, width, height);

  // Copy image data to array
  cudaMemcpyToArray(cu_array, image, width*height*sizeof(float), cudaMemcpyHostToDevice);

  // Set texture parameters (default)
  tex.addressMode[0] = cudaAddressModeClamp;
  tex.addressMode[1] = cudaAddressModeClamp;
  tex.filterMode = cudaFilterModePoint;
  tex.normalized = false; // do not normalize coordinates

  // Bind the array to the texture
  cudaBindTextureToArray(tex, cu_array);

  // Run kernel
  dim3 blockDim(16, 16, 1);
  dim3 gridDim((width + blockDim.x - 1)/ blockDim.x, (height + blockDim.y - 1) / blockDim.y, 1);
  kernel<<< gridDim, blockDim, 0 >>>(d_data, height, width);

  // Unbind the array from the texture
} //end foo()

__global__ void kernel(float* odata, int height, int width)
   unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
   unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
   if (x < width && y < height) {
      float c = tex2D(tex, x, y);
      odata[y*width+x] = c;

Below is an example given in Python that computes the product of two arrays on the GPU. The unofficial Python language bindings can be obtained from PyCUDA.[22]

import pycuda.compiler as comp
import pycuda.driver as drv
import numpy
import pycuda.autoinit

mod = comp.SourceModule("""
__global__ void multiply_them(float *dest, float *a, float *b)
  const int i = threadIdx.x;
  dest[i] = a[i] * b[i];

multiply_them = mod.get_function("multiply_them")

a = numpy.random.randn(400).astype(numpy.float32)
b = numpy.random.randn(400).astype(numpy.float32)

dest = numpy.zeros_like(a)
        drv.Out(dest), drv.In(a), drv.In(b),

print dest-a*b

Additional Python bindings to simplify matrix multiplication operations can be found in the program pycublas.[23]

import numpy
from pycublas import CUBLASMatrix
A = CUBLASMatrix( numpy.mat([[1,2,3]],[[4,5,6]],numpy.float32) )
B = CUBLASMatrix( numpy.mat([[2,3]],[4,5],[[6,7]],numpy.float32) )
C = A*B
print C.np_mat()

Language bindings[edit]

Current and future usages of CUDA architecture[edit]

See also[edit]


  1. ^ Nvidia CUDA Home Page
  2. ^ a b Abi-Chahla, Fedy (June 18, 2008). "Nvidia's CUDA: The End of the CPU?". Tom's Hardware. Retrieved May 17, 2015. 
  3. ^ Shimpi, Anand Lal; Wilson, Derek (November 8, 2006). "Nvidia's GeForce 8800 (G80): GPUs Re-architected for DirectX 10". AnandTech. Retrieved May 16, 2015. 
  4. ^ CUDA LLVM Compiler
  5. ^ First OpenCL demo on a GPU on YouTube
  6. ^ DirectCompute Ocean Demo Running on Nvidia CUDA-enabled GPU on YouTube
  7. ^ Giorgos Vasiliadis; Spiros Antonatos; Michalis Polychronakis; Evangelos P. Markatos; Sotiris Ioannidis (September 2008). "Gnort: High Performance Network Intrusion Detection Using Graphics Processors" (PDF). Proceedings of the 11th International Symposium on Recent Advances in Intrusion Detection (RAID). 
  8. ^ Schatz, M.C.; Trapnell, C.; Delcher, A.L.; Varshney, A. (2007). "High-throughput sequence alignment using Graphics Processing Units". BMC Bioinformatics. 8:474: 474. doi:10.1186/1471-2105-8-474. PMC 2222658free to read. PMID 18070356. 
  9. ^ Manavski, Svetlin A.; Giorgio Valle (2008). "CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment". BMC Bioinformatics. 9: S10. doi:10.1186/1471-2105-9-S2-S10. PMC 2323659free to read. PMID 18387198. 
  10. ^ Pyrit – Google Code
  11. ^ Use your Nvidia GPU for scientific computing, BOINC official site (December 18, 2008)
  12. ^ Nvidia CUDA Software Development Kit (CUDA SDK) – Release Notes Version 2.0 for MAC OS X
  13. ^ CUDA 1.1 – Now on Mac OS X- (Posted on Feb 14, 2008)
  14. ^ Silberstein, Mark; Schuster, Assaf; Geiger, Dan; Patney, Anjul; Owens, John D. (2008). Efficient computation of sum-products on GPUs through software-managed cache. Proceedings of the 22nd annual international conference on Supercomputing - ICS '08. pp. 309–318. doi:10.1145/1375527.1375572. ISBN 978-1-60558-158-3. 
  15. ^ NVCC forces c++ compilation of .cu files
  16. ^ C++ keywords on CUDA C code
  17. ^ "CUDA-Enabled Products". CUDA Zone. Nvidia Corporation. Retrieved 2008-11-03. 
  18. ^ Whitehead, Nathan; Fit-Florea, Alex. "Precision & Performance: Floating Point and IEEE 754 Compliance for Nvidia GPUs" (PDF). Nvidia. Retrieved November 18, 2014. 
  19. ^ ALUs perform only single-precision floating-point arithmetics. There is 1 double-precision floating-point unit.
  20. ^ No more than one scheduler can issue 2 instructions at once. The first scheduler is in charge of warps with odd IDs. The second scheduler is in charge of warps with even IDs.
  21. ^ Appendix F. Features and Technical Specifications PDF (3.2 MiB), Page 148 of 175 (Version 5.0 October 2012)
  22. ^ PyCUDA
  23. ^ pycublas
  24. ^ "MATLAB Adds GPGPU Support". 2010-09-20. 

External links[edit]