|Type of RAM|
|Type||Synchronous dynamic random-access memory|
|Clock rate||100–266 MHz|
|Cycle time||10–3.75 ns|
|Bus clock rate||200–533 MHz|
|Transfer rate||400–1066 MT/s|
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DDR3 SDRAM (launched in 2007). DDR2 DIMMs are neither forward compatible with DDR3 nor backward compatible with DDR.
In addition to double pumping the data bus as in DDR SDRAM (transferring data on the rising and falling edges of the bus clock signal), DDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus. The two factors combine to produce a total of four data transfers per internal clock cycle.
Since the DDR2 internal clock runs at half the DDR external clock rate, DDR2 memory operating at the same external data bus clock rate as DDR results in DDR2 being able to provide the same bandwidth but with better latency. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules. The maximum capacity on commercially available DDR2 DIMMs is 8GB, but chipset support and availability for those DIMMs is sparse and more common 2GB per DIMM are used.
DDR2 SDRAM was first produced by Samsung in 2001. In 2003, the JEDEC standards organization presented Samsung with its Technical Recognition Award for the company's efforts in developing and standardizing DDR2.
DDR2 was officially introduced in the second quarter of 2003 at two initial clock rates: 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR technology tops out at a clock rate around 200 MHz (400 MT/s). Higher performance DDR chips exist, but JEDEC has stated that they will not be standardized. These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer. Such chips draw significantly more power than slower-clocked chips, but usually offered little or no improvement in real-world performance. DDR2 started to become competitive against the older DDR standard by the end of 2004, as modules with lower latencies became available.
The key difference between DDR2 and DDR SDRAM is the increase in prefetch length. In DDR SDRAM, the prefetch length was two bits for every bit in a word; whereas it is four bits in DDR2 SDRAM. During an access, four bits were read or written to or from a four-bit-deep prefetch queue. This queue received or transmitted its data over the data bus in two data bus clock cycles (each clock cycle transferred two bits of data). Increasing the prefetch length allowed DDR2 SDRAM to double the rate at which data could be transferred over the data bus without a corresponding doubling in the rate at which the DRAM array could be accessed. DDR2 SDRAM was designed with such a scheme to avoid an excessive increase in power consumption.
DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is four bits deep, whereas it is two bits deep for DDR. While DDR SDRAM has typical read latencies of between two and three bus cycles, DDR2 may have read latencies between three and nine cycles, although the typical range is between four and six. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.
Another cost of the increased bandwidth is the requirement that the chips are packaged in a more expensive and difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR SDRAM and SDR SDRAM. This packaging change was necessary to maintain signal integrity at higher bus speeds.
Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates.
According to JEDEC the maximum recommended voltage is 1.9 volts and should be considered the absolute maximum when memory stability is an issue (such as in servers or other mission critical devices). In addition, JEDEC states that memory modules must withstand up to 2.3 volts before incurring permanent damage (although they may not actually function correctly at that level).
Chips and modules
For use in computers, DDR2 SDRAM is supplied in DIMMs with 240 pins and a single locating notch. Laptop DDR2 SO-DIMMs have 200 pins and often come identified by an additional S in their designation. DIMMs are identified by their peak transfer capacity (often called bandwidth).
|Standard||Type||Module||Clock rate (MHz)||Cycle time (ns)||Clock rate (MHz)||Transfer rate (MT/s)||Bandwidth (MB/s)||CL-TRCD-TRP||CAS latency (ns)|
* Some manufacturers label their DDR2 modules as PC2-4300, PC2-5400 or PC2-8600 instead of the respective names suggested by JEDEC. At least one manufacturer has reported this reflects successful testing at a higher-than-standard data rate whilst others simply round up for the name.
Note: DDR2-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC2-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
In addition to bandwidth and capacity variants, modules can:
- Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200 ECC is a PC2-4200 module with ECC. An additional P can be added at the end of the designation, P standing for parity (ex : PC2-5300P).
- unbuffered") RAM may be identified by an additional U in the designation. PC2-4200R is a registered PC2-4200 module, PC2-4200R ECC is the same module but with additional ECC.
- Be aware fully buffered modules, which are designated by F or FB do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.
- Registered and un-buffered SDRAM generally cannot be mixed on the same channel.
- The highest-rated DDR2 modules in 2009 operate at 533 MHz (1066 MT/s), compared to the highest-rated DDR modules operating at 200 MHz (400 MT/s). At the same time, the CAS latency of 11.2 ns = 6 / (bus clock rate) for the best PC2-8500 modules is comparable to that of 10 ns = 4 / (bus clock rate) for the best PC-3200 modules.
DDR2 DIMMs are not backward compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position from DDR DIMMs, and the pin density is higher than DDR DIMMs in desktops. DDR2 is a 240-pin module, DDR is a 184-pin module. Notebooks have 200-pin SO-DIMMs for DDR and DDR2; however, the notch on DDR2 modules is in a slightly different position than on DDR modules.
Higher-speed DDR2 DIMMs can be mixed with lower-speed DDR2 DIMMs, although the memory controller will operate all DIMMs at same speed as the lowest-speed DIMM present.
Relation to GDDR memory
GDDR2, a form of GDDR SDRAM, was developed by Samsung and introduced in July 2002. The first commercial product to claim using the "DDR2" technology was the Nvidia GeForce FX 5800 graphics card. However, it is important to note that this GDDR2 memory used on graphics cards is not DDR2 per se, but rather an early midpoint between DDR and DDR2 technologies. Using "DDR2" to refer to GDDR2 is a colloquial misnomer. In particular, the performance-enhancing doubling of the I/O clock rate is missing. It had severe overheating issues due to the nominal DDR voltages. ATI has since designed the GDDR technology further into GDDR3, which is based on DDR2 SDRAM, though with several additions suited for graphics cards.
GDDR3 and GDDR5 is now commonly used in modern graphics cards and some tablet PCs. However, further confusion has been added to the mix with the appearance of budget and mid-range graphics cards which claim to use "GDDR2". These cards actually use standard DDR2 chips designed for use as main system memory although operating with higher latencies to achieve higher clockrates. These chips cannot achieve the clock rates of GDDR3 but are inexpensive and fast enough to be used as memory on mid-range cards.
- DDR SDRAM
- CAS latency (definition of "CAS 5-5-5-15", for example)
- Dual-channel architecture
- Fully Buffered DIMM
- Unbuffered memory
- List of device bandwidths
- DDR3 SDRAM
- "Samsung Demonstrates World's First DDR 3 Memory Prototype". Phys.org. 17 February 2005. Retrieved 23 June 2019.
- Ilya Gavrichenkov. "DDR2 vs. DDR: Revenge gained". X-bit Laboratories. Archived from the original on 2006-11-21.
- JEDEC JESD 208 (section 5, tables 15 and 16)
- Cycle time is the inverse of the I/O bus clock frequency; e.g., 1/(100 MHz) = 10 ns per clock cycle.
- "DDR2 SDRAM SPECIFICATION" (PDF). JESD79-2E. JEDEC. April 2008: 78. Retrieved 2009-03-14. Cite journal requires
- "SPECIALITY DDR2-1066 SDRAM" (PDF). JEDEC. November 2007: 70. Retrieved 2009-03-14. Cite journal requires
- Mushkin PC2-5300 vs. Corsair PC2-5400
- "Samsung Electronics Announces JEDEC-Compliant 256Mb GDDR2 for 3D Graphics". Samsung Electronics. Samsung. 23 August 2003. Retrieved 26 June 2019.
- JEDEC standard: DDR2 SDRAM Specification: JESD79-2F, November 2009 ** http://www.jedec.org/standards-documents/docs/jesd-79-2e
- JEDEC standard: DDR2-1066 **
- "JEDEC Standard No. 21C: 4.20.13 240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification" **
- JEDEC Solid State Technology Association
- Razak Mohammed Ali. "DDR2 SDRAM interfaces for next-gen systems" (PDF). Electronic Engineering Times. Archived from the original (PDF) on 2007-09-26.
Note**: JEDEC website requires registration ($2,500 membership) for viewing or downloading of these documents: http://www.jedec.org/standards-documents