|Type||Synchronous dynamic random-access memory (SDRAM)|
|Release date||September 2014|
|Predecessor||DDR3 SDRAM (2007)|
|Successor||DDR5 SDRAM (2020)|
In computing, DDR4 SDRAM, an abbreviation for double data rate fourth-generation synchronous dynamic random-access memory, is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface.
Released to the market in 2014, it is one of the latest variants of dynamic random-access memory (DRAM), some of which have been in use since the early 1970s, and a higher-speed successor to the DDR2 and DDR3 technologies.
DDR4 is not compatible with any earlier type of random access memory (RAM) due to different signaling voltages, physical interface and other factors.
DDR4 SDRAM was released to the public market in Q2 2014, focusing on ECC memory, while the non-ECC DDR4 modules became available in Q3 2014, accompanying the launch of Haswell-E processors that require DDR4 memory.
The primary advantages of DDR4 over its predecessor, DDR3, include higher module density and lower voltage requirements, coupled with higher data rate transfer speeds. The DDR4 standard theoretically allows for DIMMs of up to 512 GiB in capacity, compared to DDR3's theoretical maximum of 128 GiB per DIMM.
DDR4 operates at a voltage between 1.2 V and 1.4 V with a frequency between 800 and 4266 MHz, compared to frequencies between 400 and 1067 MHz[a] and voltage requirements of 1.5 or 1.65 V of DDR3. Due to the nature of DDR, speeds are typically advertised as doubles of these numbers (DDR3-1600 and DDR4-2400 are common). Although a low-voltage standard has yet to be finalized (as of August 2014[update]), it is anticipated that low-voltage DDR4 will run at a voltage of 1.05 V, compared to DDR3's low-voltage standard (DDR3L) which requires 1.35 V to operate.
Standards body JEDEC began working on a successor to DDR3 around 2005, about 2 years before the launch of DDR3 in 2007. The high-level architecture of DDR4 was planned for completion in 2008.
Some advance information was published in 2007, and a guest speaker from Qimonda provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum (IDF). DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.
Subsequently, further details were revealed at MemCon 2010, Tokyo (a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4" with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably or definitely delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.
DDR4 was expected to represent 5% of the DRAM market in 2013, and to reach mass market adoption and 50% market penetration around 2015; as of 2013, however, adoption of DDR4 has been delayed and it is no longer expected to reach a majority of the market until 2016 or later. The transition from DDR3 to DDR4 is thus taking longer than the approximately five years taken for DDR3 to achieve mass market transition over DDR2. In part, this is because changes required to other components would affect all other parts of computer systems, which would need to be updated to work with DDR4.
In February 2009, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since in 2009, DRAM chips were only beginning to migrate to a 50 nm process. In January 2011, Samsung announced the completion and release for testing of a 2 GiB DDR4 DRAM module based on a process between 30 and 39 nm. It has a maximum data transfer rate of 2133 MT/s at 1.2 V, uses pseudo open drain technology (adapted from graphics DDR memory) and draws 40% less power than an equivalent DDR3 module.
In April 2011, Hynix announced the production of 2 GiB DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified), adding that it anticipated commencing high volume production in the second half of 2012. Semiconductor processes for DDR4 are expected to transition to sub-30 nm at some point between late 2012 and 2014.
In July 2012, Samsung Electronics Co., Ltd., announced that it has begun sampling the industry's first 16 GiB registered dual inline memory modules (RDIMMs) using DDR4 SDRAM for enterprise server systems.
In September 2012, JEDEC released the final specification of DDR4.
In April 2014, Hynix announced that it has developed the world's first highest-density 128 GiB module based on 8 Gib DDR4 using 20 nm technology. The module works at 2133 MHz, with a 64-bit I/O, and processes up to 17 GB of data per second. Hynix expects DDR4 SDRAM to be commercialized by 2015, and turned into a standard by 2016.
In April 2016, Samsung announced that they had begun to mass-produce DRAM on a "10nm-class" process, by which they mean the 1xnm node regime of 16 nm to 19 nm, which supports a 30% faster data transfer rate of 3,200 megabits per second. Previously, a size 20 nm was used.
Market perception and adoption
In April 2013, a news writer at International Data Group (IDG)—an American technology research business originally part of IDC—produced an analysis of their perceptions related to DDR4 SDRAM. The conclusions were that the increasing popularity of mobile computing and other devices using slower but low-powered memory, the slowing of growth in the traditional desktop computing sector, and the consolidation of the memory manufacturing marketplace, meant that margins on RAM were tight.
As a result, the desired premium pricing for the new technology was harder to achieve, and capacity had shifted to other sectors. SDRAM manufacturers and chipset creators were, to an extent, "stuck between a rock and a hard place" where "nobody wants to pay a premium for DDR4 products, and manufacturers don't want to make the memory if they are not going to get a premium", according to Mike Howard from iSuppli. A switch in market sentiment toward desktop computing and release of processors having DDR4 support by Intel and AMD could therefore potentially lead to "aggressive" growth.
||This section needs to be updated. (January 2014)|
DDR4 chips use a 1.2 V supply:16 with a 2.5 V auxiliary supply for wordline boost called VPP,:16 as compared with the standard 1.5 V of DDR3 chips, with lower voltage variants at 1.05 V appearing in 2013. DDR4 is expected to be introduced at transfer rates of 2133 MT/s,:18 estimated to rise to a potential 4266 MT/s by 2013. The minimum transfer rate of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 MT/s, left little commercial benefit to specifying DDR4 below this speed. Techgage interpreted Samsung's January 2011 engineering sample as having CAS latency of 13 clock cycles, described as being comparable to the move from DDR2 to DDR3.
Internal banks are increased to 16 (4 bank select bits), with up to 8 ranks per DIMM.:16
Protocol changes include::20
- Parity on the command/address bus
- Data bus inversion (like GDDR4)
- CRC on the data bus
- Independent programming of individual DRAMs on a DIMM, to allow better control of on-die termination.
Increased memory density is anticipated, possibly using TSV ("through-silicon via") or other 3D stacking processes. The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC, with provision for up to 8 stacked dies.:12 X-bit Labs predicted that "as a result DDR4 memory chips with very high density will become relatively inexpensive". Prefetch remains at 8n:16 with bank groups, including the use of two or four selectable bank groups.
In 2008 concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pumps and voltage regulators, and additional circuitry "have allowed significant increases in bandwidth but they consume much more die area". Examples include CRC error-detection, on-die termination, burst hardware, programmable pipelines, low impedance, and increasing need for sense amps (attributed to a decline in bits per bitline due to low voltage). The authors noted that, as a result, the amount of die used for the memory array itself has declined over time from 70–78% with SDRAM and DDR1, to 47% for DDR2, to 38% for DDR3 and potentially to less than 30% for DDR4.
The specification defined standards for ×4, ×8 and ×16 memory devices with capacities of 2, 4, 8 and 16 Gib.
Although it still operates in fundamentally the same way, DDR4 makes one major change to the command formats used by previous SDRAM generations. A new command signal, ACT, is low to indicate the activate (open row) command.
The activate command requires more address bits than any other (18 row address bits in an 8 Gb part), so the standard RAS, CAS, and WE active low signals are shared with high-order address bits that are not used when ACT is high. The combination of RAS=L, CAS=H and WE=H that previously encoded an activate command is unused.
As in previous SDRAM encodings, A10 is used to select command variants: auto-precharge on read and write commands, and one bank vs. all banks for the precharge command. It also selects two variants of the ZQ calibration command.
In addition, A12 is used to request burst chop: truncation of an 8-transfer burst after four transfers. Although the bank is still busy and unavailable for other commands until eight transfer times have elapsed, a different bank can be accessed.
Also, the number of bank addresses has been increased greatly. There are four bank select bits to select up to 16 banks within each DRAM: two bank address bits (BA0, BA1), and two bank group bits (BG0, BG1). There are additional timing restrictions when accessing banks within the same bank group; it is faster to access a bank in a different bank group.
In addition, there are three chip select signals (C0, C1, C2), allowing up to eight stacked chips to be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to 7 (128 possible banks).
|Deselect (no operation)||H||X|
|Active (activate): open a row||L||Bank||L||Row address|
|Read (BC, burst chop)||L||Bank||H||V||H||L||H||V||BC||V||AP||Column|
|Write (AP, auto-precharge)||L||Bank||H||V||H||L||L||V||BC||V||AP||Column|
|Precharge all banks||L||V||H||V||L||H||L||V||H||V|
|Precharge one bank||L||Bank||H||V||L||H||L||V||L||V|
|Mode register set (MR0–MR6)||L||L||Register||H||L||L||L||L||L||Data|
- Signal level
- H, high
- L, low
- V, either low or high, a valid signal
- X, irrelevant
- Logic level
- Not interpreted
Standard transfer rates are 1600, 1866, 2133 and 2400 MT/s. (12/15, 14/15, 16/15 and 18/15 GHz clock speeds, double data rate.) 2666 and 3200 MT/s (20/15 and 24/15 GHz clock speeds) are provided for, but the specifications are not yet complete.
- VrefDQ calibration (DDR4 "requires that VrefDQ calibration be performed by the controller");
- New addressing schemes ("bank grouping", ACT to replace RAS, CAS, and WE commands, PAR and Alert for error checking and DBI for data bus inversion);
- New power saving features (low-power auto self-refresh, temperature-controlled refresh, fine-granularity refresh, data-bus inversion, and CMD/ADDR latency).
Circuit board design:
- New power supplies (VDD/VDDQ at 1.2 V and wordline boost, known as VPP, at 2.5 V);
- VrefDQ must be supplied internal to the DRAM while VrefCA is supplied externally from the board;
- DQ pins terminate high using pseudo-open-drain I/O (this differs from the CA pins in DDR3 which are center-tapped to VTT).
DDR4 memory is supplied in 288-pin dual in-line memory modules (DIMMs), similar in size to 240-pin DDR3 DIMMs. The pins are spaced more closely (0.85 mm instead of 1.0) to fit the increased number within the same 5¼ inch (133.35 mm) standard DIMM length, but the height is increased slightly (31.25 mm/1.23 in instead of 30.35 mm/1.2 in) to make signal routing easier, and the thickness is also increased (to 1.2 mm from 1.0) to accommodate more signal layers. DDR4 DIMM modules have a slightly curved edge connector so not all of the pins are engaged at the same time during module insertion, lowering the insertion force.
For its Skylake microarchitecture, Intel designed a SO-DIMM package named UniDIMM, which can be populated with either DDR3 or DDR4 chips. At the same time, the integrated memory controller (IMC) of Skylake CPUs is announced to be capable of working with either type of memory. The purpose of UniDIMMs is to help in the market transition from DDR3 to DDR4, where pricing and availability may make it undesirable to switch the RAM type. UniDIMMs have the same dimensions and number of pins as regular DDR4 SO-DIMMs, but the edge connector's notch is placed differently to avoid accidental use in incompatible DDR4 SO-DIMM sockets.
- CAS Latency (CL)
- Clock cycles between sending a column address to the memory and the beginning of the data in response
- Clock cycles between row activate and reads/writes
- Clock cycles between row precharge and activate
DDR4-xxxx and PC4-xxxx both denote per-bit data transfer rate, the former for DDR chips and the latter for modules (assembled DIMMs). Module peak transfer rate is calculated by taking transfers per second and multiplying by eight. This is because DDR4 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
At the 2016 Intel Developer Forum the future of DDR5 SDRAM was discussed. The specifications should be finalised by the end of 2016 – but no modules available before 2020. Other memory technologies aiming to replace DDR4 have also been proposed.
In 2011, JEDEC published the Wide I/O 2 standard; it stacks multiple memory dies, but does that directly on top of the CPU and in the same package. This memory layout provides higher bandwidth and better power performance than DDR4 SDRAM, and allows a wide interface with short signal lengths. It primarily aims to replace various mobile DDRX SDRAM standards used in high-performance embedded and mobile devices, such as smartphones. Hynix proposed similar High Bandwidth Memory (HBM), which was published as JEDEC JESD235. Both Wide I/O 2 and HBM use a very wide parallel memory interface, up to 512 bits wide for Wide I/O 2 (compared to 64 bits for DDR4), running at a lower frequency than DDR4. Wide I/O 2 is targeted at high-performance compact devices such as smartphones, where it will be integrated into the processor or system on a chip (SoC) packages. HBM is targeted at graphics memory and general computing, while HMC targets high-end servers and enterprise applications.
Micron Technology's Hybrid Memory Cube (HMC) stacked memory uses a serial interface. Many other computer buses have migrated towards replacing parallel buses with serial buses, for example by the evolution of Serial ATA replacing Parallel ATA, PCI Express replacing PCI, and serial ports replacing parallel ports. In general, serial buses are easier to scale up and have fewer wires/traces, making circuit boards using them easier to design.
In the longer term, experts speculate that non-volatile RAM types like PCM (phase-change memory), RRAM (resistive random-access memory), or MRAM (magnetoresistive random-access memory) could replace DDR4 SDRAM and its successors.
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- As a prototype, this DDR4 memory module has a flat edge connector at the bottom, while production DDR4 DIMM modules have a slightly curved edge connector so not all of the pins are engaged at a time during module insertion, lowering the insertion force.
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