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Double Data Rate 5 Synchronous Dynamic Random-Access Memory
Type of RAM
TypeSynchronous dynamic random-access memory
Generation5th generation
Release dateJuly 14, 2020 (2020-07-14)[1]
Voltage1.1 V
PredecessorDDR4 SDRAM

Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 is planned to reduce power consumption, while doubling bandwidth.[2] The standard, originally targeted for 2018,[3] was released on 14 July 2020.[1]

A new feature called Decision Feedback Equalization (DFE) enables IO speed scalability for higher bandwidth and performance improvement. DDR5 supports more bandwidth than its predecessor, DDR4, with 4.8 gigabits per second possible — but not shipping at launch.[4] DDR5 will have about the same latency as DDR4 and DDR3.[5]

Rambus announced a working DDR5 DIMM in September 2017.[6][7] On November 15, 2018, SK Hynix announced completion of its first DDR5 RAM chip; it runs at 5200 MT/s at 1.1 V.[8] In February 2019, SK Hynix announced a 6400 MT/s chip, the highest speed officially allowed by the preliminary DDR5 standard.[9] Some companies were planning to bring the first products to market by the end of 2019.[10] The world's first DDR5 DRAM chip was officially launched by SK Hynix on October 6th, 2020.[11][12]

The separate JEDEC standard LP-DDR5 (Low Power Double Data Rate 5), intended for laptops and smartphones, was released in February 2019.[13]

Compared to DDR4, DDR5 further reduces memory voltage to 1.1 V, thus reducing power consumption. DDR5 modules can incorporate on-board voltage regulators in order to reach higher speeds; but as this will increase cost, it is expected to be implemented only on server-grade and possibly high-end consumer modules.[7] DDR5 supports a speed of 51.2 GB/s per module[14] and 2 memory channels per module.[15][16]

There is a general expectation that most use-cases that currently use DDR4 will eventually migrate to DDR5. To be usable in desktops and servers (laptops will presumably use LPDDR5 instead), the integrated memory controllers of e.g. Intel's and AMD's CPUs will have to support it; as of June 2020, there have not been any official announcements of support from either. Intel’s 11th-gen Rocket Lake CPUs and AMD's Ryzen 5000-series CPUs both still use DDR4 RAM.[17] A leaked internal AMD roadmap is reported to show DDR5 support for 2022 Zen 4 CPUs and Zen 3+ APUs.[18] A leaked slide shows planned DDR5 support on Intel's 2021 Sapphire Rapids microarchitecture and Alder Lake microarchitecture.[19]

DIMMs versus memory chips[edit]

While previous SDRAM generations allowed unbuffered DIMMs that consisted of memory chips and passive wiring (plus a small serial presence detect ROM), DDR5 DIMMs require additional active circuitry, making the interface to the DIMM different from the interface to the RAM chips themselves.

DDR5 DIMMs are supplied with bulk power at 12 V and management interface power at 3.3 V,[20] and use on-board circuitry (a power management integrated circuit[21] and associated passive components) to convert to the lower voltage required by the memory chips. Final voltage regulation close to the point of use provides more stable power, and mirrors the development of voltage regulator modules for CPU power supplies.

All DDR5 DIMMs are registered;[citation needed] a "registered clock driver" (RCD) chip converts a 7-bit-wide double data rate command/address bus to the DIMM to the 14-bit-wide single data rate command/address signals expected by the DRAM chips.

Unlike DDR4, all DDR5 DIMMs will have in-chip ECC, where errors are detected and corrected before sending data to the CPU. There will still exist non-ECC and ECC DDR5 DIMM variants; the ECC variants will have extra data lines to the CPU to send error detection data, enabling the CPU to detect and correct errors that occurred in transit.[citation needed]

Each DIMM has two independent channels. While earlier SDRAM generations had one CA[vague] bus controlling 64 or 72 (non-ECC/ECC) data lines, each DDR5 DIMM has two CA buses controlling 32 or 40 (non-ECC/ECC) data lines each, for a total of 64 or 80 data lines. This 4-byte bus width times a doubled minimum burst length of 16 preserves the minimum access size of 64 bytes, which matches the cache line size used by x86 microprocessors.[citation needed]


Standard DDR5 memory speeds range from 4800 to 6400 million transfers per second (PC5-38400 to PC5-51200). Higher speeds may be added later, as happened with previous generations.

Compared to DDR4 SDRAM, the minimum burst length was doubled to 16, with the option of "burst chop" after 8 transfers. The addressing range is also slightly extended as follows:

  • The number of chip ID bits remains at 3, allowing up to 8 stacked chips.
  • A third bank group bit (BG2) was added, allowing up to 8 bank groups.
  • The maximum number of banks per bank group remains at 4.
  • The number of row address bits remains at 17, for a maximum of 128K rows.
  • One more column address bit (C10) is added, allowing up to 8192 columns (1 KB pages) in ×4 chips.
  • The least-significant three column address bits (C0, C1, C2) are removed; all reads and write must begin at a column address which is a multiple of 8.
  • One bit is reserved for addressing expansion as either a fourth chip ID bit (CID3) or an additional row address bit (R17).

Command encoding[edit]

DDR5 command encoding[22][final standard verification needed]
Command CS Command/address (CA) bits
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Active (activate)
Open a row
L L L Row R0–3 Bank Bank group Chip CID0–2
H Row R4–16 R17/
Unassigned, reserved L L H V
Unassigned, reserved L H L L L V
Write pattern L H L L H L H Bank Bank group Chip CID0–2
H V Column C3–10 V AP H V CID3
Unassigned, reserved L H L L H H V
Mode register write L H L H L L Address MRA0–7 V
H Data MRD0–7 V CW V
Mode register read L H L H L H Address MRA0–7 V
Write L H L H H L BL Bank Bank group Chip CID0–2
H V Column C3–10 V AP WRP V CID3
Read L H L H H H BL Bank Bank group Chip CID0–2
H V Column C3–10 V AP V CID3
Vref CA L H H L L L Data V
Refresh all L H H L L H CID3 V L Chip CID0–2
Refresh same bank L H H L L H CID3 Bank V H Chip CID0–2
Precharge all L H H L H L CID3 V L Chip CID0–2
Precharge same bank L H H L H L CID3 Bank V H Chip CID0–2
Precharge L H H L H H CID3 Bank Bank group Chip CID0–2
Unassigned, reserved L H H H L L V
Self-refresh entry L H H H L H V L V
Power-down entry L H H H L H V H ODT V
Multi-purpose command L H H H H L Command CMD0–7 V
Power-down exit,
No operation
Deselect (no operation) H X
  • Signal level
    • H, high
    • L, low
    • V, valid, either low or high
    • X, irrelevant
  • Logic level
    •   Active
    •   Inactive
    •   Unused
  • Control bits
    • AP, Auto-precharge
    • CW, Control word
    • BL, Burst length ≠ 16
    • WRP, Write partial
    • ODT, ODT remains enabled

The command encoding was significantly rearranged and takes inspiration from that of LP-DDR4; commands are sent using either one or two cycles with 14-bit bus. Some simple commands (e.g. precharge) take one cycle, while any that include an address (activate, read, write) use two cycles to include 28 bits of information.

Also like LPDDR, there are now 256× 8-bit mode registers, rather than 8× 13-bit registers. And rather than one register (MR7) being reserved for use by the registered clock driver chip, a complete second bank of mode registers is defined (selected using the CW bit).

The "Write Pattern" command is new for DDR5; this is identical to a write command, but no data is transmitted. Instead, the range is filled with copies of a 1-byte mode register (which defaults to all-zero). Although this takes the same amount of time as a normal write, not driving the data lines saves energy. Also, writes to multiple banks may be interleaved more closely.

The multi-purpose command includes various subcommands for training and calibration of the data bus.


  1. ^ a b Smith, Ryan (July 14, 2020). "DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond". AnandTech. Retrieved July 15, 2020.
  2. ^ Manion, Wayne (March 31, 2017). "DDR5 will boost bandwidth and lower power consumption". Tech Report. Retrieved April 1, 2017.
  3. ^ Cunningham, Andrew (March 31, 2017). "Next-generation DDR5 RAM will double the speed of DDR4 in 2018". Ars Technica. Retrieved January 15, 2018.
  4. ^ "New DDR5 SDRAM standard supports double the bandwidth of DDR4". AppleInsider. Retrieved July 21, 2020.
  5. ^ Dr. Ian Cutress. "Insights into DDR5 Sub-timings and Latencies". Anandtech.
  6. ^ Lilly, Paul (September 22, 2017). "DDR5 memory is twice as fast as DDR4 and slated for 2019". PC Gamer. Retrieved January 15, 2018.
  7. ^ a b Tyson, Mark (September 22, 2017). "Rambus announces industry's first fully functional DDR5 DIMM - RAM - News". hexus.net.
  8. ^ Malakar, Abhishek (November 18, 2018). "SK Hynix Develops First 16 Gb DDR5-5200 Memory Chip". Archived from the original on March 31, 2019. Retrieved November 18, 2018.
  9. ^ Shilov, Anton. "SK Hynix Details DDR5-6400". www.anandtech.com.
  10. ^ "SK Hynix, Samsung Detail the DDR5 Products Arriving This Year". Tom's Hardware. February 23, 2019.
  11. ^ "SK hynix Launches World's First DDR5 DRAM". www.hpcwire.com.
  12. ^ "SK hynix: DDR5 DRAM Launches". businesskorea.co.kr.
  13. ^ "JEDEC Updates Standard for Low Power Memory Devices: LPDDR5" (Press release). JEDEC. February 19, 2019.
  14. ^ Lilly, Paul (September 22, 2017). "DDR5 memory is twice as fast as DDR4 and slated for 2019".
  15. ^ "What We Know About DDR5 So Far". Tom's Hardware. June 7, 2019.
  16. ^ "DDR5 - The Definitive Guide!". April 27, 2019.
  17. ^ Lisa, Su (October 28, 2020) [2020]. "AMD - Ryzen 5 5600X Desktop Processors". AMD Official. Archived from the original on October 28, 2020. Retrieved October 28, 2020.
  18. ^ "HW News - Supercomputer Cryptomining Malware, DDR5 & AMD, Ryzen 3 1200 AF". Gamers Nexus.
  19. ^ Verheyde 2019-05-22T16:50:03Z, Arne. "Leaked Intel Server Roadmap Shows DDR5, PCIe 5.0 in 2021, Granite Rapids in 2022". Tom's Hardware.
  20. ^ "P8900 PMIC for DDR5 RDIMMs and LRDIMMs". Renesas. Retrieved July 19, 2020.
    "P8911 PMIC for Client DDR5 Memory Modules". Renesas. Retrieved July 19, 2020.
  21. ^ US application 2019/0340142, Patel, Shwetal Arvind; Zhang, Andy & Meng, Wen Jie et al., "DDR5 PMIC Interface Protocol and Operation", published 2019-11-07, assigned to Integrated Device Technology, Inc. 
  22. ^ "DDR5 Full Spec Draft Rev0.1" (PDF). JEDEC committee JC42.3. December 4, 2017. Retrieved July 19, 2020.

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