|Type of RAM|
|Type||Synchronous dynamic random-access memory|
|Release date||July 14, 2020|
Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 is planned to reduce power consumption, while doubling bandwidth. The standard, originally targeted for 2018, was released on 14 July 2020.
A new feature called Decision Feedback Equalization (DFE) enables IO speed scalability for higher bandwidth and performance improvement. DDR5 supports more bandwidth than its predecessor, DDR4, with 4.8 gigabits per second possible — but not shipping at launch. DDR5 will have about the same latency as DDR4 and DDR3.
Rambus announced a working DDR5 DIMM in September 2017. On November 15, 2018, SK Hynix announced completion of its first DDR5 RAM chip; it runs at 5200 MT/s at 1.1 V. In February 2019, SK Hynix announced a 6400 MT/s chip, the highest speed officially allowed by the preliminary DDR5 standard. Some companies were planning to bring the first products to market by the end of 2019. The world's first DDR5 DRAM chip was officially launched by SK Hynix on October 6th, 2020.
Compared to DDR4, DDR5 further reduces memory voltage to 1.1 V, thus reducing power consumption. DDR5 modules can incorporate on-board voltage regulators in order to reach higher speeds; but as this will increase cost, it is expected to be implemented only on server-grade and possibly high-end consumer modules. DDR5 supports a speed of 51.2 GB/s per module and 2 memory channels per module.
There is a general expectation that most use-cases that currently use DDR4 will eventually migrate to DDR5. To be usable in desktops and servers (laptops will presumably use LPDDR5 instead), the integrated memory controllers of e.g. Intel's and AMD's CPUs will have to support it; as of June 2020, there have not been any official announcements of support from either. Intel’s 11th-gen Rocket Lake CPUs and AMD's Ryzen 5000-series CPUs both still use DDR4 RAM. A leaked internal AMD roadmap is reported to show DDR5 support for 2022 Zen 4 CPUs and Zen 3+ APUs. A leaked slide shows planned DDR5 support on Intel's 2021 Sapphire Rapids microarchitecture and Alder Lake microarchitecture.
DIMMs versus memory chips
While previous SDRAM generations allowed unbuffered DIMMs that consisted of memory chips and passive wiring (plus a small serial presence detect ROM), DDR5 DIMMs require additional active circuitry, making the interface to the DIMM different from the interface to the RAM chips themselves.
DDR5 DIMMs are supplied with bulk power at 12 V and management interface power at 3.3 V, and use on-board circuitry (a power management integrated circuit and associated passive components) to convert to the lower voltage required by the memory chips. Final voltage regulation close to the point of use provides more stable power, and mirrors the development of voltage regulator modules for CPU power supplies.
All DDR5 DIMMs are registered; a "registered clock driver" (RCD) chip converts a 7-bit-wide double data rate command/address bus to the DIMM to the 14-bit-wide single data rate command/address signals expected by the DRAM chips.
Unlike DDR4, all DDR5 DIMMs will have in-chip ECC, where errors are detected and corrected before sending data to the CPU. There will still exist non-ECC and ECC DDR5 DIMM variants; the ECC variants will have extra data lines to the CPU to send error detection data, enabling the CPU to detect and correct errors that occurred in transit.
Each DIMM has two independent channels. While earlier SDRAM generations had one CA[vague] bus controlling 64 or 72 (non-ECC/ECC) data lines, each DDR5 DIMM has two CA buses controlling 32 or 40 (non-ECC/ECC) data lines each, for a total of 64 or 80 data lines. This 4-byte bus width times a doubled minimum burst length of 16 preserves the minimum access size of 64 bytes, which matches the cache line size used by x86 microprocessors.
Standard DDR5 memory speeds range from 4800 to 6400 million transfers per second (PC5-38400 to PC5-51200). Higher speeds may be added later, as happened with previous generations.
Compared to DDR4 SDRAM, the minimum burst length was doubled to 16, with the option of "burst chop" after 8 transfers. The addressing range is also slightly extended as follows:
- The number of chip ID bits remains at 3, allowing up to 8 stacked chips.
- A third bank group bit (BG2) was added, allowing up to 8 bank groups.
- The maximum number of banks per bank group remains at 4.
- The number of row address bits remains at 17, for a maximum of 128K rows.
- One more column address bit (C10) is added, allowing up to 8192 columns (1 KB pages) in ×4 chips.
- The least-significant three column address bits (C0, C1, C2) are removed; all reads and write must begin at a column address which is a multiple of 8.
- One bit is reserved for addressing expansion as either a fourth chip ID bit (CID3) or an additional row address bit (R17).
|Command||CS||Command/address (CA) bits|
Open a row
|L||L||L||Row R0–3||Bank||Bank group||Chip CID0–2|
|Write pattern||L||H||L||L||H||L||H||Bank||Bank group||Chip CID0–2|
|Mode register write||L||H||L||H||L||L||Address MRA0–7||V|
|Mode register read||L||H||L||H||L||H||Address MRA0–7||V|
|Write||L||H||L||H||H||L||BL||Bank||Bank group||Chip CID0–2|
|Read||L||H||L||H||H||H||BL||Bank||Bank group||Chip CID0–2|
|Refresh all||L||H||H||L||L||H||CID3||V||L||Chip CID0–2|
|Refresh same bank||L||H||H||L||L||H||CID3||Bank||V||H||Chip CID0–2|
|Precharge all||L||H||H||L||H||L||CID3||V||L||Chip CID0–2|
|Precharge same bank||L||H||H||L||H||L||CID3||Bank||V||H||Chip CID0–2|
|Precharge||L||H||H||L||H||H||CID3||Bank||Bank group||Chip CID0–2|
|Multi-purpose command||L||H||H||H||H||L||Command CMD0–7||V|
|Deselect (no operation)||H||X|
The command encoding was significantly rearranged and takes inspiration from that of LP-DDR4; commands are sent using either one or two cycles with 14-bit bus. Some simple commands (e.g. precharge) take one cycle, while any that include an address (activate, read, write) use two cycles to include 28 bits of information.
Also like LPDDR, there are now 256× 8-bit mode registers, rather than 8× 13-bit registers. And rather than one register (MR7) being reserved for use by the registered clock driver chip, a complete second bank of mode registers is defined (selected using the CW bit).
The "Write Pattern" command is new for DDR5; this is identical to a write command, but no data is transmitted. Instead, the range is filled with copies of a 1-byte mode register (which defaults to all-zero). Although this takes the same amount of time as a normal write, not driving the data lines saves energy. Also, writes to multiple banks may be interleaved more closely.
The multi-purpose command includes various subcommands for training and calibration of the data bus.
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- "P8900 PMIC for DDR5 RDIMMs and LRDIMMs". Renesas. Retrieved July 19, 2020.
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- US application 2019/0340142, Patel, Shwetal Arvind; Zhang, Andy & Meng, Wen Jie et al., "DDR5 PMIC Interface Protocol and Operation", published 2019-11-07, assigned to Integrated Device Technology, Inc.
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