The DECstation was a brand of computers used by DEC, and refers to three distinct lines of computer systems—the first released in 1978 as a word processing system, and the latter (more widely known) two both released in 1989. These comprised a range of computer workstations based on the MIPS architecture and a range of PC compatibles. The MIPS-based workstations ran Ultrix, a DEC-proprietary version of UNIX, and early releases of OSF/1.
DECstation RISC workstations
The second (and completely unrelated) line of DECstations began with the DECstation 3100, which was released on 11 January 1989. The DECstation 3100 was the first commercially available RISC-based machine built by DEC.
This line of DECstations was the fruit of an advanced development skunkworks project carried out in DEC's Palo Alto Hamilton Ave facility. Known as the PMAX project, its focus was to produce a computer systems family with the economics and performance to compete against the likes of Sun Microsystems and other RISC-based UNIX platforms of the day. The brainchild of James Billmaier, Mario Pagliaro, Armando Stettner and Joseph DiNucci, the systems family was to also employ a truly RISC-based architecture when compared to the heavier and very CISC VAX or the then still under development Prism architectures. At the time DEC was mostly known for their CISC systems including the successful PDP and VAX lines.
Several architectures were considered from Intel, Motorola and others but the group quickly selected the MIPS line of microprocessors. The (early) MIPS microprocessors supported both big- and little-endian modes (configured during hardware reset). Little-endian mode was chosen both to match the byte ordering of VAX-based systems and the growing number of Intel-based PCs and computers.
In contrast to the VAX and the later DEC Alpha architectures, the DECstation 3100 and family were specifically designed and built to run a UNIX system, Ultrix, and no version of the VMS operating system was ever released for DECstations. One of the issues being debated at the project's inception was whether or not DEC could sustain, grow, and compete with an architecture it did not invent or own (manage). As the core advocates later left the company, the MIPS-based line of computers was shut down in favor of the Alpha-based computers, a DEC invented and owned architecture, descended from the Prism development work.
The first generation of commercially marketed DEC Alpha systems, the DEC 3000 AXP series, were similar in some respects to contemporaneous MIPS-based DECstations, which were sold alongside the Alpha systems as the DECstation line was gradually phased out. Both used the TURBOchannel expansion bus for video and network cards, as well as being sold with the same TURBOchannel option modules, mice, monitors, and keyboards.
Later DECstations planned to be based on the ECL-based R6000 were canceled on 14 August 1990 after Bipolar Integrated Technology failed to deliver sufficient volumes of the microprocessor, which was difficult to fabricate. Yields of the R6000 were further reduced as DEC required the little-endian mode used from the beginning to continue to be available.
The MIPS-based DECstations were used as the first target system and development platform for the Mach microkernel, as well as early development of the Windows NT operating system. Shortly prior to the release of the DEC Alpha systems, a port of OSF/1 to the DECstation was completed, but it was not commercially released. More recently, various free operating systems such as NetBSD and Linux/MIPS have been ported to the MIPS-based DECstations, extending their useful life by providing a modern operating system.
The GXemul project emulates several of these DECstation models.
The original MIPS-based DECstation 3100 was followed by a cost reduced 2100. The DECstation 3100 was claimed to be the world's fastest UNIX workstation at the time. When it was introduced it was about three times as fast as the VAXstation 3100 which was introduced at about the same time. Server configurations of DECstation models, distributed without a framebuffer or a graphics accelerator, both Turbochannel and Q-bus based, were called "DECsystem" but should not be confused with some PDP-10 machines of the same name.
Early models of the DECstation were heavily integrated systems with little expansion capability and do not even possess expansion buses. The DECstation 5000 systems, introduced later, improved on the lack of expansion capabilities by providing the TURBOchannel Interconnect. The DECstation 5000 systems are also ARC (Advanced RISC Computing) compatible. The last DECstation models focused on increased component integration by using more custom ASICs to reduce the number of discrete components. This begun with the DECstation 5000 Model 240, which replaced discrete components with LSI ASICs and ended with the last model, the DECstation 5000 Model 260, which used a single VLSI ASIC for much of the control logic.
Packaged DECstation 5000 systems were sometimes suffixed with two or three letters. These letters refer to what graphics option the system has.
DECstation 3100 and DECstation 2100
|Model and codename||Processor||MHz||Introduced||Withdrawn|
|3100 "PMAX"||R2000, R2010, R2020 chipset||16.67 MHz (60 ns)||11 January 1989||?|
|2100 "PMIN"||R2000, R2010, R2020 chipset||12.50 MHz (80 ns)||11 July 1989||?|
The DECstation 3100 and 2100 uses a R2000 processor, a R2010 floating point coprocessor and four R2020 write buffers. The R2000 uses an external 64 KB direct-mapped instruction cache and a 64 KB direct-mapped write-through data cache with a cache line size of four bytes. Four R2020 implement a four-stage write buffer to improve performance by permitting the R2000 to write to its write-through data cache without stalling.
The R2000 microprocessor could be configured to run either in big-endian or little-endian mode. In the DECstation family, the decision was made to run little-endian to maintain compatibility with both the VAX family and the growing population of Intel-based PC's.
The DECstation 3100 and 2100's memory system contains both the DRAM-based system memory and VRAM-based framebuffers. The amount of system memory supported is 4 to 24 MB, organized into six physical memory banks. These systems has 12 SIMM slots that use 2 MB SIMMs, with each SIMM containing 1,048,576 word × 18-bit DRAMs. The SIMMs are installed in pairs (in increments of 4 MB) and the memory system is byte-parity protected. The monochrome framebuffer are implemented with a 256 KB VFB01 SIMM and the color framebuffer, a 1 MB VBF02 SIMM. If one of these framebuffer SIMMs are not present, the framebuffer cannot be used. The SIMM slots were rated for 25 removal and insertion cycles, with five being the recommended limit.
Graphics capability was provided by two frame buffer modules, the monochrome and color frame buffer. The monochrome frame buffer supports 1-bit color and a resolution of 1024 × 864 pixels, while the color frame buffer supports 8-bit color and the same resolution as the monochrome frame buffer. Both frame buffers use the Brooktree Bt478 RAMDAC with three 256-entry, 8-bit color maps. The hardware cursor is generated by DC503 PCC (Programmable Cursor Chip), which can provide a 16 × 16 pixel, 2-bit color cursor. The color frame buffer has an 8-bit write mask, used to select which pixel(s) are to be updated. None of the framebuffers use all the memory provided by the frame buffer module, the color frame buffer's VRAM is organized as 2048 × 1024 pixels and the monochrome frame buffer, 1024 × 1024, but only the leftmost pixels are displayed in the color frame buffer and the topmost pixels in the monochrome frame buffer. Unused areas of the VRAM may be used to store graphical structures such as fonts. The frame buffers are not parity-protected, unlike the rest of the system memory. A DB15 male connector is used for video. The connector uses RS343A/RS170 compatible signals.
Ethernet and SCSI
These DECstations have onboard 10 Mbit/s Ethernet provided by an AMD 7990 LANCE (Local Area Network Controller for Ethernet) and an AMD 7992 SIA (Serial Interface Adapter), which implements the interface, a BNC ThinWire Ethernet connector. A 32 768 word × 16-bit (64 KB) network buffer constructed out of SRAMs is provided to improve performance. A 32 word by 8-bit Ethernet Station Address ROM (ESAR) provides the MAC address. It is mounted in a DIP socket and is removable.
The 5 MB/s single-ended SCSI interface is provided by a DC7061 SII gate array with a 64 K by 16-bit (128 KB) SCSI buffer used to improve performance. The SCSI interface is connected to the internal 3.5 drive bays and an external port (HONDA68 male connector) to be connected to drive expansion boxes.
These systems have four asynchronous serial lines that are provided by a DC7085 gate array. Of the four serial lines, only the third line has the required modem control signals to support a modem. A 4-pin MMJ connector is provided for the keyboard line, a 7-pin DIN connector for mouse line, and two 6-pin MMJ connectors for printer and modem lines. The real time clock is a Motorola MC146818, which also has 50 bytes of RAM for storing console configuration information, and the 256 KB of ROM for storing boot-strap and self-test software is provided by two 128 KB ROMs in DIP sockets.
The enclosure used by the DECstation 3100 and 2100 is identical to the enclosure used by the VAXstation 3100 as these systems use a mechanically identical system module. The enclosure can accommodate two 3.5-inch drives, which are mounted on trays above the system module. The system module is located on the left of the enclosure and the power supply, which takes up a fourth of the space inside the enclosure, is located on the left.
Personal DECstation 5000 Series
The Personal DECstation 5000 Series are entry-level workstations, code named "MAXine". The Personal DECstation uses a low-profile desktop case, which contained a power supply on the left and two mounts for two fixed drives, or one fixed drive and one diskette drive, at the front. The system logic was contained on two printed circuit boards, the base system module, which contained the majority of the logic, and the CPU module, which contained the processor.
|Model 20||R3000A, R3010 chipset||20||28 January 1994|
|Model 25||R3000A, R3010 chipset||25||28 January 1994|
|Model 33||R3000A, R3010 chipset||33||22 June 1992||28 January 1994|
|Model 50||R4000||100||28 January 1994|
There were three models of the CPU module, which contains the CPU subsystem. The first model contains a chipset consisting of a 20, 25 or 33 MHz R3000A CPU and R3010 FPU accompanied by a 64 KB instruction cache and a 64 KB data cache. Both caches are direct-mapped and have a 4-byte cache line. The data cache is write through. All components on the CPU module operate at the same clock frequency as the R300A.
A CPUCTL ASIC is also present, its purpose to provide interfacing and buffering between the faster CPU module and the slower 12.5 MHz system module. The CPUCTL ASIC also implements a 12.5 MHz TURBOchannel that serves as the system interconnect.
The second model is a revised version of the first module with a 20 or 25 MHz R3000A and R3010 that used plastic packaging, whereas the previous model used ceramic packaging. The third model contains a R4000 microprocessor with internal instruction and data caches complemented by a 1 MB secondary cache.
These systems have 8 MB of onboard memory and four SIMM slots that can be used to expand the amount of memory by 32 MB, for a total of 40 MB of memory. These SIMM slots accept 2 and 8 MB SIMMs in pairs. All SIMMs in the system must be of the same size. The memory bus is 40 bits wide, with 32 bits used for data and four bits used to for byte-parity. The Memory Control ASIC controls the memory and communicates with the CPU subsystem via the TURBOchannel bus.
Expansion is provided by two TURBOchannel slots, each with 64 MB of physical address space.
The Personal DECstation features an integrated 8-bit color frame buffer capable of a resolution of 1024 × 768 at a refresh rate of 72 Hz. The frame buffer consists of 1 MB of VRAM organized as 262,144 32-bit words, with each 32-bit word containing four 8-bit pixels. The frame buffer uses an INMOS IMS G332 RAMDAC with a 256-entry 24-bit color look up table, which selects 256 colors for display out of a palette of 16,777,216. The frame buffer is treated as part of the memory subsystem.
The I/O subsystem provides the system with an 8-bit single-ended SCSI bus, 10 Mbit/s Ethernet, serial line, the Serial Desktop Bus and analog audio. SCSI is provided by a NCR 53C94 ASC (Advanced SCSI Controller). Ethernet is provided by an AMD Am7990 LANCE (Local Area Network Controller for Ethernet) and an AMD Am7992 SIA (Serial Interface Adapter) that implements the AUI interface. A single serial port capable of 50 to 19,200 baud with full modem control capability is provided by a Zilog Z85C30 SCC (Serial Communications Controller). Analog audio and ISDN support is provided by an AMD 79C30A DSC (Digital Subscriber Controller). These devices are connected to IOCTL ASIC via two 8-bit buses or one 16-bit bus. The ASIC interfaces the subsystem to the TURBOchannel interconnect.
DECstation 5000 Model 100 Series
|Model 120||R3000A, R3010 chipset||20||?||?|
|Model 125||R3000A, R3010 chipset||25||?||?|
|Model 133||R3000A, R3010 chipset||33||?||?|
The DECstation 5000 Model 100 Series, code named "3MIN", are mid-range workstations. Early models used a chipset consisting of a R3000A CPU and a R3010 CPU on 3- by 5-inch daughter card that plugs into a connector on the system module. The Model 150 replaces the R3000A and R3010 with a single R4000 with an integrated FPU. The Model 120 and 125 have two external caches, a 64 KB instruction cache and a 64 KB data cache. The Model 133 has a 128 KB instruction cache.
These systems support 16 to 128 MB of memory through 16 SIMM slots that accept 2 or 8 MB SIMMs. Only one type of SIMM may be used, 2 and 8 MB SIMMs cannot be mixed in the same system. The 2 MB SIMM is identical to the SIMM used in the DECstation 2100 and 3100, allowing upgrades from these older systems to the Model 100 Series to reuse the old memory.
Three TURBOchannel option slots are provided. The Model 100 Series introduces the I/O Controller ASIC (later known as the IOCTL ASIC), which interfaces the two 8-bit I/O buses to the 12.5 MHz TURBOchannel.
DECstation 5000 Model 200 Series
The DECstation 200 Series are high-end workstations. Server configurations of the DECstation 500 Model 200, 240 and 260 were known as the DECsystem 5000 Model 200, 240 and 260 respectively. These systems only contain a CPU module, a system module and a power supply located on left side of the enclosure. They do not have any internal storage capability. Drives were intended to be installed in external single- or multiple-drive enclosures. These enclosures were connected to system via a SCSI connector located at the rear of the system. Alternatively, storage was to be provided by a file server accessed over a network.
|Model and codename||Processor||MHz||Introduced||Discontinued|
|Model 200 "3MAX"||R3000, R3010 chipset||25||3 April 1990||?|
|Model 240 "3MAX+"||R3400||40||?||No earlier than September 1994|
|Model 260 "3MAX+"||R4400||120||?||?|
Each member of the Model 200 Series had a unique CPU subsystem. The Model 200's CPU subsystem is located on the KN02 system module and contains a chipset composed of the R3000 CPU, R3010 FPU and R3220 MB (six-stage write/memory buffer). Also part of the subsystem is the processor's external 64 KB instruction cache and 64 KB write-through data cache. In contrast, the Model 240's CPU subsystem is located on a daughter card, the CPU module, and does not use a processor chipset, featuring a single 40 MHz R3400 instead. The R3400 integrates the R3000A CPU and the R3010 FPU in a single die and package. The processor's external 64 KB instruction cache and 64 KB data cache is connected to the R3400 by a 40 MHz bus that also serves as the datapath to the MB ASIC. The Model 260's CPU subsystem is also located on a CPU module daughter card, but it features a 120 MHz (60 MHz external) R4000 with internal instruction and data caches and an external secondary cache. The Model 260's CPU subsystem is unique in the Model 200 Series as it contains the boot ROM firmware, unlike the other members, which have their boot ROM located in the system module. This difference is due to the R4000 requiring different firmware that could not be replaced when upgrading a Model 240 to a Model 260.
The Model 200 Series has 15 SIMM slots located on the system module that can hold 8 to 480 MB of memory. Proprietary 128-pin memory array modules (SIMMs) with capacities of 8 MB (39 1 Mbit DRAM chips) or 32 MB (39 4 Mbit DRAM chips) are used. All SIMMs installed in a system must be of the same size. If 8 MB SIMMs are used, the system may contain 8 to 120 MB of memory. If 32 MB SIMMs are used, the system may contain 32 to 480 MB of memory. The memory subsystem operates at 25 MHz and is 32 bits wide to match the native word length of the R3000. The memory subsystem is protected by an ECC scheme with seven bits of check for every 32-bit transaction.
The SIMMs are two-way interleaved using the low-order method, where even and odd memory addresses are treated as separate banks of memory. Interleaving the memory subsystem doubles the bandwidth of a non-interleaved memory subsystem using the same DRAMs, allowing the Model 200 Series to achieve an effective maximum bandwidth of 100 MB/s.
An optional 1 MB NVRAM module that provides a disk cache to improve performance can be installed in one of the SIMM slots (slot 14, the SIMM slot closest to the front edge of the system module). The module uses a battery to prevent data from being lost in case of power failure. The module is useful only when optional software is installed.
The Model 200 uses discrete components to implement the memory subsystem logic. In the Model 240, these discrete components are replaced by three ASICs, the MB ASIC, the MT ASIC and the MS ASIC. The MB (Memory Buffer) ASIC serves as an interface between the 40 MHz CPU module domain and the 25 MHz system module domain. It is connected to the MT ASIC, which serves as the memory controller. The MT ASIC provides memory control and refresh, handles memory DMA and transactions, and ECC checking. The MS (Memory Strobe) ASIC provides 15 sets of memory control lines and routes memory control signals from the MT ASIC to the destination SIMM. The MS ASIC replaces 16 discrete components used in the Model 200 and also generates the 25 MHz system clock signal, replacing a further three discrete components used in the Model 200.
The Model 200 Series uses the TURBOchannel Interconnect for expansion and all models have three TURBOchannel option slots. The Model 200 provides 4 MB of physical address space for each TURBOchannel option, while the Model 240 and 260 provides 8 MB. TURBOchannel in the Model 240 and 260 is clocked at 25 MHz. In the Model 240 and 260, the MT ASIC implements TURBOchannel and serves as the controller.
The Model 200's I/O subsystem is significantly different from the Model 240 and 260's I/O subsystem. In the Model 200, Ethernet and SCSI capabilities are provided by two integrated TURBOchannel option modules, PMAD-AA for Ethernet and PMAZ-AA for SCSI. The PMAD-AA uses an AMD 7990 LANCE (Local Area Network Controller for Ethernet), which provides 10BASE-T Ethernet. The interface is implemented by an AMD 7992 SIA (Serial Interface Adapter) and a BNC ThinWire connector. The 8-bit, single-ended SCSI bus is provided by an NCR 53C94 ASC (Advanced SCSI Controller). Both integrated option modules have 128 KB of SRAM each serving as a buffer to improve performance. Four serial lines are also provided for the keyboard, mouse, communications port and printer. These lines are implemented by two DC7085s. A Dallas Semiconductor DS1287 real time clock with 50 bytes of NVRAM is also featured, as is a 256 KB system boot-strap and diagnostic ROM in a socket.
In contrast, the Model 240's and 260's I/O subsystem is based around an I/O Controller ASIC that serves as a bridge between TURBOchannel and the two I/O buses it implements. I/O devices such as the two Zilog Z85C30 SCCs (Serial Communications Controller), a NCR 53C94 ASC, an AMD 7990 LANCE, Dallas Semiconductor DS1287 real time clock and system ROM are connected to the I/O buses. The I/O Controller ASIC was not introduced by the Model 240, it was first featured in the Model 100 series, but the ASIC used in the Model 240 differs by being clocked twice as high, at 25 MHz instead of 12.5 MHz. The Model 240's I/O subsystem would later be used in the DEC 3000 AXP in a modified form.
DECstation systems with TURBOchannel slots could use TURBOchannel-based framebuffers, 2D graphics accelerators and 3D graphics accelerators.
- CX "Color Frame-Buffer Graphics Module", model PMAG-BA. It was capable of 8-bit color at a resolution of 1024 × 864.
- HX "Smart Frame-Buffer Graphics Module", models PMAGB-BA/BC/BE. The HX is a framebuffer with a custom ASIC with limited, but very fast, 2D acceleration capabilities.
- MX "Monochrome Frame-Buffer Graphics Module", model PMAG-AA. The MX is capable of 1-bit color at a resolution of 1280 × 1024 with a refresh rate of 72 Hz.
- TX "True Color Frame-Buffer Graphics Module", models PMAG-JA, PMAGB-JA. Both models were capable of 24-bit color at a resolution of 1280 × 1024. The two models differ only in refresh rate, the PMAG-JA had a 66 Hz refresh rate and the PMAGB-JA, 72 Hz.
2D graphics accelerators
- PX "2D Graphics Accelerator". The PX was based on the PixelStamp architecture, but without the geometry engine, meaning that it could only accelerate 2D graphics. It was superseded by the HX at some point in most applications.
3D graphics accelerators
These options were:
- The PXG, also known as the "Lo 3D Graphics Accelerator" or the "Mid 3D Graphics Accelerator" depending on configuration
- The PXG+, also known as the "Lo 3D Plus Graphics Accelerator" or the "Mid 3D Plus Graphics Accelerator" depending on configuration
- The PXG Turbo, also known as the "Hi 3D Graphics Accelerator"
- The PXG Turbo+, also known as the "Hi 3D Plus Graphics Accelerator"
All PXG variants are capable of either 8-bit or 24-bit color, a resolution of 1280 × 1024 and a refresh rate of either 66 or 72 Hz. The PXG also has an 8-bit or 24-bit Z-buffer and is double buffered. The color depth and the depth of Z-buffer can be extended by installing additional VSIMMs or Z-buffer modules on the module. The PXG Turbo variants are capable of 24-bit color, a resolution of 1280 × 1024 and a refresh rate of either 66 or 72 Hz. They differ by featuring a 24-bit buffer for storing off-screen pixmaps in addition to the 24-bit Z-buffer and double buffer.
These 3D graphics accelerators implemented Digital's proprietary PixelStamp architecture, which is derived from two research projects, Pixel Planes from the University of North Carolina and The 8 by 8 Display from the Carnegie-Mellon University.
The PixelStamp architecture is a geometry pipeline that consists of a DMA engine, a geometry engine and a PixelStamp. The DMA engine interfaces the pipeline to the system via TURBOchannel, receiving packets from the CPU and sending them to the geometry engine. The geometry engine consists of an amount of SRAM and an Intel i860. Packets from the DMA engine are stored in the SRAM, where they are processed by the i860, which writes the results to a FIFO.
The PixelStamp consists of a STIC (STamp Interface Chip) ASIC and one or two STAMP ASICs. The STIC fetches the results in the FIFO and passes them on to the STAMP ASIC(s), which performs scan conversion and other graphical functions. Once the data has been processed by the STAMP ASICs, the final result, which consists of RGB data, is written into the framebuffer built from VSIMMs (a SIMM with VRAMs) that are located on the graphics accelerator option module to be displayed.
These graphics accelerators can be grouped into two distinct categories, the double-width options and the triple-width options. The PXG and PXG+ are double-width TURBOchannel option modules and the PXG Turbo and PXG Turbo+ are triple-width TURBOchannel option modules. Models suffixed with a "+" are higher performance models of the base model, with a 44 MHz i860 instead of a 40 MHz i860 and STIC and STAMP ASICs that operate at clock frequencies 33% higher. Models suffixed with "Turbo" differ by featuring 256 KB of SRAM and two STAMP ASICs instead of 128 KB of SRAM and one STAMP ASIC. Models known as a "Lo 3D Graphics Accelerator" or a "Lo 3D Plus Graphics Accelerator" can be upgraded to a "Mid 3D Graphics Accelerator" or a "Mid 3D Plus Graphics Accelerator" by installing more VSIMMs and Z-buffer modules.
Depending on the model of DECstation, some systems were capable of performing video conferencing, high-quality audio output and video input. These were achieved through the use of TURBOchannel option modules and external peripherals. Video input was achieved by using the DECvideo (also known as the PIP (Picture-in-Picture) live-video-in) option, a daughterboard that plugs into the TX framebuffer to provide NTSC, PAL and SECAM input. When this option was used in conjunction with a video camera, a microphone and the required software, the DECstation can be used for video conferencing.
Audio capabilities were provided by the DECaudio TURBOchannel option module, which contained two AMD 79C30A DSC (Digital Subscriber Controller) devices and a Motorola 56001 DSP. The two AMD 79C30A DSCs were used for voice-quality audio input and output, while the Motorola 56001 was used for high-quality audio. The DSP was initially not used, due to the firmware being incomplete, although the capability was provided later in an update.
Confusingly, simultaneous with the launch of the DECstation workstation line, Digital also announced a range of DECstation-branded PC compatibles with Intel x86 processors that ran MS-DOS. These were identified by three-digit model numbers; the DECstation 2xx, 3xx and 4xx series using the Intel 80286, 80386 and 80486 processors respectively. These computers were not built by Digital, but by Tandy Corporation in the United States and Olivetti in Europe. At the time of introduction, Digital offered a trade-in program for owners of its earlier x86, but PC incompatible, computer, the Rainbow 100.
Systems based on the 80286 are:
- DECstation 210
- DECstation 220
- DECstation 212
- DECstation 212LP
Systems based on the 80386 are:
- DECstation 316
- DECstation 316+
- DECstation 316sx
- DECstation 320
- DECstation 320+
- DECstation 320sx
- DECstation 325c
- DECstation 333c
Systems based on the 80486 are:
- DECstation 420sx
- DECstation 425c
- DECstation 433T
- DECstation 433W
- DECstation 450dx2
- Thomas C. Furlong et al., "Development of the DECstation 3100". Digital Technical Journal, Volume 2, Number 2, Spring 1990. Digital Equipment Corporation
- Armando Stettner
- "DEC Cancels ULTRIX Workstation Using ECL R6000". Computer Business Review, 15 August 1990.
- Workstation Systems Engineering: "DECstation 3100 Desktop Workstation Functional Specification", Revision 1.3, 28 August 1990, Digital Equipment Corporation
- John Markoff: "COMPANY NEWS; 8 Desktop Computers Introduced by Digital," New York Times
- RISC Family Performance Summary, 2 April 1990, Digital Equipment Corporation
- When used in the context of semiconductor memory, 1 KB refers to 210 (1,024) bytes and 1 MB refers to 220 (1,048,576) bytes
- Personal DECstation/DECsystem 5000 Series Maintenance Guide, Third Printing, April 1993, EK-PM30F-MG-004, Digital Equipment Corporation[permanent dead link]
- Worksystems Base Product Marketing: "Personal DECstation Series Technical Overview", Version 1.0, December 1991, Digital Equipment Corporation
- DECstation 5000/100 Series Workstations, Digital Equipment Corporation
- Worksystems Base Product Marketing: "DECstation 5000 Model 240 Workstation Technical Overview", Version 1.0, December 1991, Digital Equipment Corporation
- DECstation/DECsystem 5000 Model 200 Series Maintenance Guide, Second Printing, April 1993, EK-PM38C-MG-002, Digital Equipment Corporation
- Todd A. Dutton et al., "The Design of the DEC 3000 AXP Systems, Two High-performance Workstations", Digital Technical Journal, Volume 4, Number 4, Special Issue 1992.
- TURBOchannel Maintenance Guide, October 1991, EK-TRBOC-MG-005, Digital Equipment Corporation[permanent dead link]
- Joel McCormack and Bob McNamara. WRL Research Report 93/1, A Smart Frame Buffer. Western Research Laboratory, Digital Equipment Corporation.
- Brian Kelleher. PixelVision Architecture. Workstation Systems Engineering, Digital Equipment Corporation.