# Digital delay line

A digital delay line (or simply delay line, also called delay filter) is a discrete element in a digital filter, which allows a signal to be delayed by a number of samples. Delay lines are commonly used to delay audio signals feeding loudspeakers to compensate for the speed of sound in air, and to align video signals with accompanying audio, called audio-to-video synchronization. Delay lines may compensate for electronic processing latency so that multiple signals leave a device simultaneously despite having different pathways.

Digital delay lines are widely used building blocks in methods to simulate room acoustics, musical instruments and effects units. Digital waveguide synthesis shows how digital delay lines can be used as sound synthesis methods for various musical instruments such as string instruments and wind instruments.

If a delay line holds a non-integer value smaller than one, it results in a fractional delay line (also called interpolated delay line or fractional delay filter). A series of an integer delay line and a fractional delay filter is commonly used for modelling arbitrary delay filters in digital signal processing. The Dattorro scheme is an industry standard implementation of digital filters using fractional delay lines.

## Theory

The standard delay line with integer delay is derived from the Z-transform of a discrete-time signal $x$ delayed by $M$ samples:

$y[n]=x[n-M]$ ${\xrightarrow[{}]{\mathcal {Z}}}$ $Y(z)=\overbrace {z^{-M}} ^{H_{M}(z)}X(z).$ In this case, $z^{-M}=H_{M}(z)$ is the integer delay filter with:

${\begin{cases}|\centerdot |=1=0dB,&{\text{zero dB gain}}\\\measuredangle =-\omega M,&{\text{linear phase with }}\omega =2\pi fT_{s}{\text{ where }}T_{s}{\text{ is the sampling period in seconds }}[s].\end{cases}}$ The discrete-time domain filter for integer delay $M$ as the inverse zeta transform of $H_{M}(z)$ is trivial, since it is an impulse shifted by $M$ :

$h_{m}[n]={\begin{cases}{\text{1}},&{\text{for }}n=M\\0,&{\text{for }}n\neq M.\end{cases}}$ Working in the discrete-time domain with fractional delays is less trivial. In its most general theoretical form, a delay line with arbitrary fractional delay is defined as a standard delay line with delay $D\in \mathbb {R}$ , which can be modelled as the sum of an integer component $M\in \mathbb {Z}$ and a fractional component $d\in \mathbb {R}$ which is smaller than one sample:

(Fractional) Delay Line - ${\mathcal {Z}}$ Domain
$H_{D}(z)=z^{-D}\;\;\;\;\;{\text{where}}\;\;\;\;\;D=\overbrace {\lfloor D\rfloor } ^{M}+\overbrace {(D-\lfloor D\rfloor )} ^{d}$ (Def. 1)

This is the ${\mathcal {Z}}$ domain representation of a non-trivial digital filter design problem: the solution is an any time-domain filter that represents or approximates the inverse Z-transform of $H_{D}(z)$ .

## Filter design solutions

### Naive solution

The conceptually easiest solution is obtained by sampling the continuous-time domain solution, which is trivial for any delay value. Given a continuous-time signal $x$ delayed by $D\in \mathbb {R}$ samples, or $\tau =DT_{s}$ seconds:

$y(t)=x(t-D)$ ${\xrightarrow[{}]{\mathcal {F}}}$ $Y(\omega )=\overbrace {e^{-j\omega D}} ^{H_{ideal}(\omega )}X(\omega ).$ In this case, $e^{-j\omega D}=H_{ideal}(\omega )$ is the continuous-time domain fractional delay filter with:

${\begin{cases}|\centerdot |=1=0dB,&{\text{zero dB gain}}\\\measuredangle =-\omega D,&{\text{linear phase}}\\\tau _{gr}=-{d\measuredangle \over {d\omega }}=D,&{\text{constant group delay}}\\\tau _{ph}=-{\measuredangle \over {\omega }}=-D,&{\text{constant phase delay.}}\end{cases}}$ The naive solution for the sampled filter $h_{ideal}[n]$ is the sampled inverse Fourier transform of $H_{ideal}(\omega )$ , which produces a non-causal IIR filter shaped as a Cardinal Sine $sinc()$ shifted by $D$ :

$h_{ideal}[n]={\mathcal {F}}^{-1}[H_{ideal}(\omega )]={1 \over {2\pi }}\int \limits _{-\pi }^{+\pi }e^{j\omega D}e^{j\omega n}d\omega =sinc(n-D)={sin(\pi (n-D)) \over {\pi (n-D)}}$ The continuous-time domain $sinc$ is shifted by the fractional delay while the sampling is always aligned to the cartesian plane, therefore:

• when the delay is an integer number of samples $D\in \mathbb {N}$ , the sampled shifted $sinc$ degenerates to a shifted impulse just like in the theoretical solution.
• when the delay is a fractional number of samples $D\in \mathbb {R}$ , the sampled shifted $sinc$ produces a non-causal IIR filter, which is not implementable in practice. The ideal fractional delay line is obtained by sampling the inverse Fourier transform of the continuous-time domain fractional delay filter. Note how for integer delay value this case degenerates to simple shifted impulses. Delaying a sampled signal with this filter conceptually coincides to resampling its analog source with equal sampling period but sample alignment shifted by D ∈ R {\displaystyle D\in \mathbb {R} } . Also note that the image shows only the few samples around zero, but the non-causal IIR is defined for an infinite number of samples in both directions of the x-axis.

### Truncated causal FIR solution

The conceptually easiest implementable solution is the causal truncation of the naive solution above.

$h_{\tau }[n]={\begin{cases}sinc(n-D)&{\text{for }}0\leq n\leq N\\0&{\text{otherwise}}\end{cases}}\;\;\;\;\;{\text{where}}\;\;\;\;\;{N-1 \over {2}} Truncating the impulse response might however cause instability, which can be mitigated in a few ways:

• Windowing the truncated impulse response, therefore smoothing it. Note that in this case we have to add a further shift $L$ in order to align the window and the $sinc()$ and provide symmetric filtering.

$h_{\tau }[n]={\begin{cases}w(n-D)sinc(n-D)&{\text{for }}L\leq n\leq L+N\\0&{\text{otherwise}}\end{cases}}\;\;\;\;\;{\text{where}}\;\;\;\;\;L={\begin{cases}round(D)-{N \over {2}}&{\text{for even }}N\\\lfloor D\rfloor -{N-1 \over {2}}&{\text{for odd }}N\end{cases}}$ • General Least Square (GLS) Method: iteratively adjusts the frequency response by windowing a Least Square Integral Error design, which minimises the square integral error between ideal and truncated frequency responses of the filter, defined as:

$E_{LS}={1 \over {2\pi }}\int \limits _{-\alpha \pi }^{\alpha \pi }w(\omega )|H_{D}^{truncated}(e^{j\omega })-H_{D}^{id}(e^{j\omega })|^{2}d\omega \;\;\;\;\;{\text{where }}0<\alpha \leq 1{\text{ is the passband width parameter}}$ • Lagrange Interpolator (Maximally Flat Fractional Delay Filter): adds "flatness" constraints to the first N derivatives of the Least Square Integral Error. This method is of particular interest because it has a closed form solution:

$h_{D}[n]=\prod _{k=0,\;k\neq n}^{N}{D-k \over {n-k}}\;\;\;\;\;{\text{where}}\;\;\;\;\;0\leq n\leq N$ What follows is an expansion of the formula above displaying the resulting filters of order up to $N=3$ :

Lagrange Interpolator Formula Expansion
$h_{\tau }$ $h_{\tau }$ $h_{\tau }$ $h_{\tau }$ N = 1 $1-D$ $D$ - -
N = 2 ${(D-1)(D-2) \over {2}}$ $-D(D-2)$ ${D(D-1) \over {2}}$ -
N = 3 $-{(D-1)(D-2)(D-3) \over {6}}$ ${D(D-2)(D-3) \over {2}}$ $-{D(D-1)(D-3) \over {2}}$ ${D(D-1)(D-2) \over {6}}$ ### All-pass IIR phase-approximated solution

Another approach is designing an IIR filter of order $N$ with a Z-transform structure that forces it to be an all-pass while still approximating a $D$ delay:

$H_{D}(z)={z^{-N}A(z) \over {A(z^{-1})}}={a_{N}+a_{N-1}z^{-1}+...+a_{1}z^{-(N-1)}+z^{-N} \over {1+a_{1}z^{-1}+...+a_{N-1}z^{-(N-1)}+a_{N}z^{-N}}}\;\;\;\;\;{\text{which has}}\;\;\;\;\;{\begin{cases}|\centerdot |=1=0dB&0dB{\text{ gain}}\\\measuredangle _{H_{D}(z)}=-N\omega +2\measuredangle _{A(z)}=-D\omega &{\text{desired value for delay }}D\end{cases}}$ The reciprocally placed zeros and poles of $A(z){\text{ and }}A(z^{-}1)$ respectively flatten the frequency $|\centerdot |$ response, while the phase is function of the phase of $A(z)$ . Therefore, the problem becomes designing the FIR filter $A(z)$ , that is finding its coefficients $a_{k}$ as a function of D (note that $a_{0}=1$ always), so that the phase approximates best the desired value $\measuredangle _{H_{D}(z)}=-D\omega$ .

The main solutions are:

• Iterative minimization of Least Square Phase Error, which is defined as:

$E_{LS}={1 \over {2\pi }}\int \limits _{-\pi }^{\pi }w(\omega )|\underbrace {\underbrace {-D\omega } _{\measuredangle _{ID}}-\underbrace {(-N\omega +2\measuredangle _{A(z)})} _{\measuredangle _{H}}} _{\Delta \measuredangle _{H_{D}}}|^{2}d\omega$ • Iterative minimization of Least Square Phase Delay Error, which is defined as:

$E_{LS}={1 \over {2\pi }}\int \limits _{-\pi }^{\pi }w(\omega )|{{\Delta \measuredangle _{H_{D}}} \over {\omega }}|^{2}$ • Thiran All-Pole Low-Pass Filter with Maximally Flat Group Delay. This yields a closed solution for finding the coefficients $a_{k}$ for positive delay $D>0$ :

$a_{k}=(-1)^{k}{\binom {N}{k}}\prod _{l=0}^{N}{D+l \over {D+k+l}}\;\;\;\;\;{\text{where}}\;\;\;\;\;{\binom {n}{k}}={N! \over {k!(N-k)!}}$ What follows is an expansion of the formula above displaying the resulting coefficients of order up to $N=3$ :

Thiran All-Pole Low-Pass Filter Coefficients Formula Expansion
$a_{0}$ $a_{1}$ $a_{2}$ $a_{3}$ N = 1 1 $-{D-1 \over {D+1}}$ - -
N = 2 1 $-2{D-2 \over {D+1}}$ ${(D-1)(D-2) \over {(D+1)(D+2)}}$ -
N = 3 1 $-3{D-3 \over {D+1}}$ $3{(D-2)(D-3) \over {(D+1)(D+2)}}$ $-{(D-1)(D-2)(D-3) \over {(D+1)(D+2)(D+3)}}$ ## Commercial history

Digital delay lines were first used to compensate for the speed of sound in air in 1973 to provide appropriate delay times for the distant speaker towers at the Summer Jam at Watkins Glen rock festival in New York, with 600,000 people in the audience. New York City–based company Eventide Clock Works provided digital delay devices each capable of 200 milliseconds of delay. Four speaker towers were placed 200 feet (60 m) from the stage, their signal delayed 175 ms to compensate for the speed of sound between the main stage speakers and the delay towers. Six more speaker towers were placed 400 feet from the stage, requiring 350 ms of delay, and a further six towers were placed 600 feet away from the stage, fed with 525 ms of delay. Each Eventide DDL 1745 module contained one hundred 1000-bit shift register chips and a bespoke digital-to-analog converter, and cost $3,800 (equivalent to$26,585 in 2022).