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Display Serial Interface

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Display Serial Interface connector on Raspberry Pi single-board computer

The Display Serial Interface (DSI) is a specification by the Mobile Industry Processor Interface (MIPI) Alliance aimed at reducing the cost of display controllers in a mobile device. It is commonly targeted at LCD and similar display technologies. It defines a serial bus and a communication protocol between the host, the source of the image data, and the device which is the destination. The interface is closed source, which means that the specification of the interface is not open to the public. The maintenance of the interface is the responsibility of the MIPI Alliance. Only legal entities (e.g., companies) can be members. These members or the persons commissioned and approved by them have access to the specification in order to use it in their possible applications.



The MIPI Alliance was formed in 2003, aiming to establish standards in mobile industry components. The first version of the MIPI DSI, version 1.0 was released in 2005. MIPI DSI v1.1 was released in 2007, and added features such as "Command Mode" for directly sending commands and data to display modules using the display controller.[1] DSI v1.2 was released in 2011, and extended the video packet length and expanded the command mode.[2] DSI v1.3 was released in 2013. DSI versions 1.4 and DSI-2 were released in 2016 and 2018 respectively.



At the physical layer, DSI specifies a high-speed (e.g., 4.5 Gbit/s/lane for D-PHY 2.0[3]) differential signaling point-to-point serial bus. This bus includes one high speed clock lane and one or more data lanes. Each lane is carried on two wires (due to differential signaling). All lanes travel from the DSI host to the DSI device, except for the first data lane (lane 0), which is capable of a bus turnaround (BTA) operation that allows it to reverse transmission direction. When more than one lane is used, they are used in parallel to transmit data, with each sequential bit in the stream traveling on the next lane. That is, if 4 lanes are being used, 4 bits are transmitted simultaneously, one on each lane. The link operates in either low power (LP) mode or high speed (HS) mode. In low power mode, the high-speed clock is disabled, and signal clocking information is embedded in the data. In this mode, the data rate is insufficient to drive a display, but is usable for sending configuration information and commands. High speed mode enables the high-speed clock (at frequencies from tens of megahertz to over one gigahertz) that acts as the bit clock for the data lanes. Clock speeds vary by the requirements of the display. High speed mode is still designed to reduce power usage due to its low voltage signaling and parallel transfer ability.

The communication protocol describes two sets of instructions. The Display Command Set (DCS) is a set of common commands for controlling the display device, and their format is specified by the DSI standard. It defines registers that can be addressed and what their operation is. It includes basic commands such as sleep, enable, and invert display. The Manufacturer Command Set (MCS) is a device-specific command space whose definition is up to the device manufacturer. It often includes commands required to program non-volatile memory, set specific device registers (such as gamma correction), or perform other actions not described in the DSI standard. The packet format of both sets is specified by the DSI standard. There are Short and Long Packets, Short Packet is 4 bytes long; Long Packet can be of any length up to 216 bytes. Packets are composed of a DataID, word count, error correction code (ECC), payload and checksum (CRC). Commands that require reading data back from the device trigger a BTA event, which allows the device to reply with the requested data. A device cannot initiate a transfer; it can only reply to host requests.

Image data on the bus is interleaved with signals for horizontal and vertical blanking intervals (porches). The data is drawn to the display in real time and not stored by the device. This allows the manufacture of simpler display devices without frame buffer memory. However, it also means that the device must be continuously refreshed (at a rate such as 30 or 60 frames per second) or it will lose the image. Image data is only sent in HS mode. When in HS mode, commands are transmitted during the vertical blanking interval.



It can be used to control displays and touch controls, often being used in smartphones, tablets, automotive dashboard display/infotainment systems.[3]

See also



  1. ^ https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/UserGuides/Microchip_UG0948_PolarFire_MIPI_DSI_Transmitter_User_Guide_V1.pdf
  2. ^ "MIPI DSI Transmitter v1.2 Controller IP, Compatible with MIPI D-PHY & C-PHY". www.design-reuse.com. Retrieved 2023-05-31.
  3. ^ a b "MIPI Display Serial Interface (MIPI DSI)". 9 December 2016.