Multiple patterning

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Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the upcoming 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.

Multiple patterning with feature coloring. Multiple patterning requires features in one layer to be colored according to their assignment in the patterning sequence. For example, here the purple, red and green indicate three separately exposed features (LELELE), while the blue features are formed by deposition in between the other features (SID SADP).

Although EUV has been projected to be the next-generation lithography of choice, it would still require more than one lithographic exposure, due to the foreseen need to first print a series of lines and then cut them.[1] It is also likely more than one cut would be needed, even for EUV.[2]

Even for electron beam lithography, single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning.[3][4]

Pitch Splitting[edit]

Pitch splitting. Each feature color represents one group of features which may be imaged at once.

The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called pitch splitting, since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20 nm and 14 nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.

Sidewall Image Transfer[edit]

Need for cutting a spacer. After a mandrel feature is patterned (a), a spacer is formed on its sidewall (b). An uncut patterned spacer forms a loop (c), which is not used as a conducting path. Therefore, some means must be found for cutting the spacer loop (d). Generally, it is an additional lithographic exposure, with another mask (called a trim mask or cut mask) used.

As pitch splitting has become more difficult due to possible differences in feature positions between different exposed parts, sidewall image transfer (SIT) has become more recognized as the necessary approach. The SIT approach typically requires a spacer layer to be formed on an etched feature's sidewall. If this spacer corresponds to a conducting feature, then ultimately it must be cut at no less than two locations to separate the feature into two or more conducting lines as typically expected. On the other hand, if the spacer corresponds to a dielectric feature, cutting would not be necessary. The prediction of how many cuts would be needed for advanced logic patterns has been a large technical challenge. Many approaches for spacer patterning have been published (some listed below), all targeting the improved management (and reduction) of the cuts.

Self-aligned contact/via patterning[edit]

Self-aligned via dual-damascene patterning.

Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells[5] and has been extended to patterning of active areas (see "Crossed self-aligned patterning" below). It is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias.[6]

Litho-Etch-Litho-Etch... (LELE...)[edit]

Double Expose, Double Etch (trenches): Photoresist coating over first pattern; etching adjacent to previous features; mask removal
Double Expose, Double Etch (lines): Photoresist coating over first pattern; photoresist features between previous features; etching; mask removal

A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.

A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography [3].


This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration.[7]

A concern with the use of this approach is the discrepancy and delay between the second photoresist pattern and the first hardmask pattern, resulting in an additional source of variation.

A variation on this approach which eliminates the first hardmask etch is resist freezing,[4] which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method,[5] where the freezing is accomplished by surface hardening of the first resist layer.

Self-Aligned Double Pattterning (SADP)[edit]

Spacer mask: first pattern; deposition; spacer formation by etching; first pattern removal; etching with spacer mask; final pattern

In spacer patterning, a spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. This is commonly referred to as Self-Aligned Doubled Patterning (SADP). The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.

As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness.[8]

The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other.[9] Any misalignment of masks or excursion in pre-patterned feature critical dimension (CD) will cause the pitch between features to alternate, a phenomenon known as pitch walking.[10]

The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned.

Spacer-is-Dielectric (SID) SADP[edit]

SID SADP for 48 nm metal pitch. 2D interconnecting patterns may be achieved without multiple block/cut masks, when the spacer surrounds metal features.
SIM vs. SID SADP. Left: Spacer-is-metal SADP may use more than one cut/block mask (red, green). Right: Spacer-is-dielectric SADP uses one cut/block mask (orange).

In self-aligned double patterning (SADP), the number of cut/block masks may be reduced or even eliminated in dense patches when the spacer is used to directly pattern inter-metal dielectric instead of metal features.[11][12] The reason is the cut/block locations in the core/mandrel features are already patterned in the first mask.

1D vs. 2D SAQP (24 nm pitch). Although 1D multiple patterning has been more commonly studied, the need for economy of block/cut exposures and added masks (numbered above) is driving the evolution toward a 2D approach, with less dense blocks/cuts and more complex mandrel (core) patterns.
Toshiba Grid Routing SAQP. One of the more recent advances in multiple patterning uses three colors with grid routing for pitch quartering, i.e., ~90 nm mandrel pitch reduced to 22-23 nm final feature pitch.

Beyond 193 nm immersion SADP[edit]

There have been numerous concerns that multiple patterning diminishes or even reverses the node-to-node cost reduction expected with Moore's Law. EUV is more expensive than three 193i exposures (i.e., LELELE), considering the throughput.[13] Moreover, EUV is more liable to print smaller mask defects not resolvable by 193i.[14]

Self-Aligned Triple Patterning (SATP)[edit]

Self-aligned triple patterning has been considered as a promising successor to SADP, due to its introduction of a second spacer offering additional 2D patterning flexibility and higher density.[15] A total of two masks (mandrel and trim) is sufficient for this approach.[16] The only added cost relative to SADP is that of depositing and etching the second spacer. The main disadvantage of SATP succeeding SATP is that it would only be usable for one node. For this reason, self-aligned quadruple patterning (SAQP) is more often considered.

Self-aligned triple patterning (SATP). Self-aligned triple patterning allows 2D flexibility without multiple block/cut masks and tighter pitch than SADP.

SAQP Grid Routing[edit]

Currently, the smallest number of masks for SAQP may be achieved by the grid routing method first described by Toshiba.[11][12][17] The number of masks used is the same as for SADP (1 mandrel/core, 1 trim/cut/block), since only SADP loop patterns need cutting. The remaining patterns do not need cutting or trimming, since they are patterned through the same initial exposure.

EUV vs. Multiple Patterning[edit]

Beyond 18 nm half-pitch, with no pellicle for EUV in its current state,[18] a cost-reduced SATP or SAQP is expected to be put in place; SAQP is already in use for NAND flash. SAQP is also able to be used from 18 to 12 nm half-pitch, while EUV cannot address the 12 nm half-pitch.

EUV cuts for 26 nm pitch lines require two masks. Due to difficulty to reach 18 nm 2D array half-pitch resolution with 0.33 NA, two EUV masks would be required for the gridded block/cut locations in this pattern.

At the 2016 EUVL Workshop, ASML reported that the 0.33 NA NXE EUV tools would not be capable of standard single exposure patterning for the 11-13 nm half-pitch expected at the 5 nm node.[19] A higher NA of 0.55 would allow single exposure EUV patterning of fields which are half the 26 mm x 33 mm standard field size.[19] However, some products, such as NVIDIA's Pascal Tesla P100,[20] will be bisected by the half-field size, and therefore require stitching of two separate exposures.[21] In any case, two half-field scans consume twice as much acceleration/deceleration overhead as a single full-field scan.[19][22]

The existing 0.33 NA EUV tools are challenged below16 nm half-pitch resolution,[23] hence more than a single EUV exposure would be needed at a minimum for the 7nm and 5nm nodes.

Directed Self-Assembly[edit]

The number of masks may be reduced with the use of directed self-assembly (DSA) due to the provision of gridded cuts all at once within a printed area, which can then be selected with a final exposure.[24][25] Alternatively, the cut pattern itself may be generated as a DSA step.[26]

As of 2010, much progress was reported on the use of PMMA-PS block copolymers to define sub-20 nm patterns by means of self-assembly, guided by surface topography (graphoepitaxy) and/or surface chemical patterning (chemoepitaxy).[27] The key benefit is the relatively simple processing, compared to multiple exposures or multiple depositions and etching. The main drawback of this technique is the relatively limited range of feature sizes and duty cycles for a given process formulation. Nevertheless, the timing for sub-20 nm node ~2013 is currently being targeted.[28] Typical applications have been regular lines and spaces as well as arrays of closely packed holes or cylinders.[29] However, random, aperiodic patterns may also be generated using carefully defined guiding patterns.[30]

The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter.[31] A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)−1/2, where a is the statistical polymer chain length.[32] Moreover, χN>>10 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π2)1/3aN2/3χ1/6. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.

Specific Implementations for Contact/Via Patterns[edit]

Merged hole separation by etch shrink[edit]

Tokyo Electron Ltd (TEL) was able to resolve two merged contact holes by applying an etch shrink.[33] 31-32 nm contact half-pitch was achieved through this method.[34]

2D SID Spacer Patterning[edit]

The use of SID may be applied to 2D arrays, by iteratively adding features equidistant from the previously present features, doubling the density with each iteration.[35]

Triangular Spacer (Honeycomb Structure) Patterning[edit]

Samsung recently demonstrated DRAM patterning using a honeycomb structure (HCS) suitable for 20 nm and beyond.[36] Each iteration of spacer patterning triples the density, effectively reducing 2D pitch by a factor of sqrt(3).

Industrial adoption[edit]

Memory patterns are already patterned by quadruple patterning for NAND[37] and crossed quadruple/double patterning for DRAM.[38] These patterning techniques are self-aligned and do not require custom cutting or trim masks.

Current EUV throughput is still more than 3x slower than 193 nm immersion lithography, thus allowing the latter to be extended by multiple patterning. Furthermore, the lack of an EUV pellicle is also prohibitive.

As of 2016, Intel is using SADP for its 10 nm node.[39] Intel is using triple patterning for some critical layers at its 14nm node,[40] which is the LELELE approach.[41] Triple patterning is already demonstrated in 10nm tapeout.[42] TSMC is deploying 7 nm in 2017 with multiple patterning.[43] Beyond the 5nm node, multiple patterning, even with EUV assistance, would be economically challenging, since the departure from EUV single exposure would drive up the cost even higher. However, at least down to 12 nm half-pitch, LELE followed by SADP (SID) appears to be the most promising approach, using only two masks, and also using the most mature double patterning techniques, LELE and SADP.[44]

LELE+SADP (SID): 2 masks for pitch quartering. LELE may be used to pattern features down to ~45 nm pitch, which then act as mandrels for subsequent SADP down to ~22 nm pitch, where the spacer surrounds the locations of the final metal features.

Patterning Costs[edit]

Cost comparison for 10nm node patterning. Process cost estimates independently provided by IBM/Cadence and TEL. See the table to the left.
Patterning Method Normalized Wafer Cost (Ref. 1) Normalized Wafer Cost (Ref. 2)
193i SE 1 1
193i LELE 2.5 2.5
193i LELELE 3.5 3.5
193i SADP 3 2
193i SAQP 4.5 3
EUV SE 3 4
EUV SADP 8 6

Refs.: (1) L. Liebmann, A. Chu and P. Gutwin, Proc. SPIE 9427, 942702 (2015); (2) A. Raley et al., Proc. SPIE 9782, 97820F (2016).

2D Multi-Patterning Options[edit]

Cost comparison for 7nm node patterning. Process cost estimates independently provided by IBM/Cadence and TEL. See table above.
Cost comparison for 5nm node patterning. Process cost estimates independently provided by IBM/Cadence and TEL. See table above.

Cutting lines to form irregular patterns uses the maximum number of masks. 2D patterning is generally preferred, but requires sufficient exposed feature pitch, followed by sufficient splitting or division of the pitch. On the other hand, LELE, LELELE, and SADP (SID) can avoid line cuts, while SATP or SAQP with grid routing can minimize line cuts. EUV 2D patterning is limited to >32 nm pitch.[45] Consequently, EUV would require double patterning for its introduction at or beyond 7nm;[46] this may prove too costly to implement against the immersion-based combination of mature double patterning techniques LELE+SADP,[44] especially the SID form of SADP,[11]with LELE and SID SADP already established for 14nm and 10nm, respectively.

Node Half-pitch ArFi EUV
14nm 32 nm LELE[47] (128 nm pitch lithography) (SE - skipped)
10nm 22-24 nm LELELE or SADP (SID)[11] (mandrel pitch = 92-96 nm) (SE - skipped)
7nm 16 nm LELE+SADP (SID)[44] or SAQP[11] (128 nm pitch lithography) LELE[19]
5nm 11-12 nm LELE+SADP (SID)[44] or SAQP[11] (88-96 nm pitch lithography) LELELE or SADP (SID) (mandrel pitch = 48 nm) or High NA x 2 Fields[19]

Notes: SE=Single Exposure (conventional lithography); LELE=Litho-(followed by)Etch 2 times; LELELE=Litho-(followed by)Etch 3 times;SADP=Self-Aligned (Spacer) Double Patterning; SID = Spacer-Is-Dielectric; SATP=Self-Aligned (Spacer) Triple Patterning; SAQP=Self-Aligned (Spacer) Quadruple Patterning

References[edit]

  1. ^ E. van Setten et al., Proc. SPIE 9661, 96610G (2015).
  2. ^ http://www.eetimes.com/document.asp?doc_id=1327919 EUV 5nm test
  3. ^ Double patterning HSQ processes of zone plates for 10 nm diffraction limited performance
  4. ^ H. Duan, et al., JVST B8, c6c58 (2010).
  5. ^ US Patent 6165880, assigned to TSMC.
  6. ^ Y. Loquet et al., Microelec. Eng. 107, 138 (2013).
  7. ^ IMEC double patterning
  8. ^ X. Hua et al., J. Vac. Sci. Tech. B, vol. 24, pp. 1850-1858 (2006).
  9. ^ Y-K Choi et al., J. Phys. Chem. B, vol. 107, pp. 3340-3343 (2003).
  10. ^ Chao, Robin; Kohli, Kriti K.; Zhang, Yunlin; Madan, Anita; Muthinti, Gangadhara Raja; Hong, Augustin J.; Conklin, David; Holt, Judson; Bailey, Todd C. (2014-01-01). "Multitechnique metrology methods for evaluating pitch walking in 14 nm and beyond FinFETs". Journal of Micro/Nanolithography, MEMS, and MOEMS. 13 (4): 041411–041411. doi:10.1117/1.JMM.13.4.041411. ISSN 1932-5150. 
  11. ^ a b c d e f C. Kodama et al., IEEE Trans. CAD Integ. Circ. and Sys., vol. 34, 753 (2015).
  12. ^ a b US Patent Application 20150021782, assigned to Kabushiki Kaisha Toshiba.
  13. ^ D. Civay et al., J. Micro/Nanolith. MEMS MOEMS 14, 023501 (2015).
  14. ^ K. Seki et al., Proc. SPIE 9658, 96580G (2015).
  15. ^ Y. Chen et al., Proc. SPIE 7973, 79731P (2011).
  16. ^ M. Mirsaeedi et al., IEEE Trans. VLSI Syst. 22, 1170 (2014).
  17. ^ K. Nakayama et al., Proc. SPIE 8327, 83270V (2012).
  18. ^ EUVL 2016 Workshop update
  19. ^ a b c d e ASML report on the high NA EUV scanner at 2016 EUVL Workshop
  20. ^ NVIDIA Pascal Tesla P100 Unveiled - 15.3 Billion Transistors on a 610mm2 16nm Die
  21. ^ Microlithography: Science and Technology, 2nd ed., B. W. Smith and K. Suzuki (eds.), CRC Press, 2007, p. 94.
  22. ^ Handbook of Semiconductor Manufacturing Technology, Y. Nishi and R. Doering (eds.), CRC Press, 2000, p. 475.
  23. ^ T-B. Chiou et al., Proc. SPIE 9781, 978107 (2016).
  24. ^ Synopsis Presentation at Semicon West 2013
  25. ^ M. C. Smayling et al., Proc. SPIE 8683, 868305 (2013).
  26. ^ Z. Xiao et al., Proc. SPIE 8880, 888017-3 (2013).
  27. ^ S. H. Park et al., Soft Matter, 6, 120-125 (2010).
  28. ^ Chipmakers Mull Plans to Insert DSA at 14 nm
  29. ^ C. G. Hardy and C. Tang, J. Polymer Sci. Pt. B: Polymer Phys., vol. 51, pp. 2-15 (2013).
  30. ^ L-W. Chang et al.IEDM 2010 Technical Digest, 752-755 (2010).
  31. ^ NIST 2011 report on LER in PS-b-PMMA DSA
  32. ^ A. N. Semenov, Macromolecules 26, 6617 (1993).
  33. ^ K. Oyama et al., Proc. SPIE 9051, 90510V (2014).
  34. ^ M. C. Smayling et al., Proc. SPIE 9426, 94261U (2015).
  35. ^ B. Mebarki et al., U. S. Patent 8,084,310, assigned to Applied Materials.
  36. ^ J. M. Park et al., IEDM 2015, 676 (2015).
  37. ^ Hynix M1X NAND
  38. ^ U.S. Patent 9318369, assigned to Samsung.
  39. ^ Intel discusses 10nm
  40. ^ Intel goes to 7nm without EUV
  41. ^ [1]
  42. ^ Triple patterning is becoming common at 10nm
  43. ^ [2]
  44. ^ a b c d F. T. Chen et al., Proc. SPIE 8683, 868311 (2013).
  45. ^ T-B. Chiou et al., Proc. SPIE 9781, 978107 (2016).
  46. ^ ASML 7nm EUV slide 46
  47. ^ H. Tomizawa et al., IITC 2011.