Multiple patterning

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Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the upcoming 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.

Self-aligned double and quadruple patterning with blocking. Above: Self-aligned double patterning (SADP) with a block mask is commonly used for 40-50 nm pitches. Below: An option for sub-40 nm pitch metal patterning (used by Intel) is to make use of self-aligned quadruple patterning (SAQP). In this example, two block patterns are used after SAQP.

Although EUV has been projected to be the next-generation lithography of choice, it would still require more than one lithographic exposure, due to the foreseen need to first print a series of lines and then cut them; a single EUV exposure pattern has difficulty with line end-to-end spacing control.[1] It is also likely more than one cut would be needed, even for EUV.[2]

Even for electron beam lithography, single exposure appears insufficient at ≈10 nm half-pitch, hence requiring double patterning.[3][4]

Pitch Splitting[edit]

LELELE pitch splitting. Each feature color represents one group of features which may be imaged at once and patterned by a standard litho-etch procedure.
2D LELELE triple patterning. Triple patterning allows some extra flexibility to insert bends for lines switching tracks.

The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called pitch splitting, since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20 nm and 14 nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.

Double Expose, Double Etch (trenches): Photoresist coating over first pattern; etching adjacent to previous features; mask removal

A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.

A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography [4].

This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration.[5]

A concern with the use of this approach is the discrepancy and delay between the second photoresist pattern and the first hardmask pattern, resulting in an additional source of variation.

A variation on this approach which eliminates the first hardmask etch is resist freezing,[5] which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method,[6] where the freezing is accomplished by surface hardening of the first resist layer.

In recent years, the scope of the term 'pitch splitting' has gradually been expanded to include techniques involving sidewall spacers.

Sidewall Image Transfer[edit]

Spacer mask: first pattern; deposition; spacer formation by etching; first pattern removal; etching with spacer mask; final pattern
SADP based on two successive depositions as well as at least two etches.

In spacer patterning, a spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. This is commonly referred to as Self-Aligned Double Patterning (SADP). The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.

Fin cuts by two masks after SAQP. A 7nm FinFET SRAM cell requires SAQP to pattern fin lines (black), which then need two additional cut masks (red, purple) to removed portions as needed.

As pitch splitting has become more difficult due to possible differences in feature positions between different exposed parts, sidewall image transfer (SIT) has become more recognized as the necessary approach. The SIT approach typically requires a spacer layer to be formed on an etched feature's sidewall. If this spacer corresponds to a conducting feature, then ultimately it must be cut at no less than two locations to separate the feature into two or more conducting lines as typically expected. On the other hand, if the spacer corresponds to a dielectric feature, cutting would not be necessary. The prediction of how many cuts would be needed for advanced logic patterns has been a large technical challenge. Many approaches for spacer patterning have been published (some listed below), all targeting the improved management (and reduction) of the cuts.

As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness.[6]

The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other.[7] Any misalignment of masks or excursion in pre-patterned feature critical dimension (CD) will cause the pitch between features to alternate, a phenomenon known as pitch walking.[8]

The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned.

When SADP is repeated, an additional halving of the pitch is achieved. This is often referred to as Self-Aligned Quadruple Patterning (SAQP). With 76 nm being the expected minimum pitch for a single immersion lithography exposure,[9] 19 nm pitch is now accessible with SAQP.

Self-aligned contact/via patterning[edit]

Self-aligned via dual-damascene patterning.

Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells[10] and is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias.[11][12][13]

Spacer-is-Dielectric (SID) SADP[edit]

Spacer-is-dielectric SADP including blocking pattern. In this example (40 nm metal pitch), the blocking pattern (yellow) comes from a second mask, since the spacer and gap formation follow the core pattern from the first mask (blue).
SID patterning for 2D patterns. Layouts with both horizontal and vertical line portions may be patterned by the SID approach. Blue: core; Red: filling of spacer gap with metal; Yellow: block.

In self-aligned double patterning (SADP), the number of cut/block masks may be reduced or even eliminated in dense patches when the spacer is used to directly pattern inter-metal dielectric instead of metal features.[14][15] The reason is the cut/block locations in the core/mandrel features are already patterned in the first mask. There are secondary features which emerge from the gaps between spacers after further patterning. The edge between a secondary feature and the spacer is self-aligned with the neighboring core feature.

Other multi-patterning techniques[edit]

There have been numerous concerns that multiple patterning diminishes or even reverses the node-to-node cost reduction expected with Moore's Law. EUV is more expensive than three 193i exposures (i.e., LELELE), considering the throughput.[16] Moreover, EUV is more liable to print smaller mask defects not resolvable by 193i.[17] Some aspects of other considered multi-patterning techniques are discussed below.

Layout Splitting[edit]

Commonly, some layers consist of patterns which require different exposure conditions, e.g., different dipole illuminations for horizontal vs. vertical features.[18] This would result in breaking the layout into two or more different masks, each with a customized illumination. More generally, this technique, applied to each mask, is called Source-Mask-Optimization (SMO). Although EUV has been targeted for single exposure patterning, the need for SMO at relatively loose design rules to address shadowing still necessitates the use of double or multiple patterning at 10 nm and beyond.[19]

Triple patterning by spacer gap splitting. The gap between spacers from SADP processing may be split to produce two additional features, resulting in effective triple patterning.

Self-Aligned Triple Patterning (SATP)[edit]

Self-aligned triple patterning has been considered as a promising successor to SADP, due to its introduction of a second spacer offering additional 2D patterning flexibility and higher density.[20][21] A total of two masks (mandrel and trim) is sufficient for this approach.[22] The only added cost relative to SADP is that of depositing and etching the second spacer. The main disadvantage of SATP succeeding SADP is that it would only be usable for one node. For this reason, self-aligned quadruple patterning (SAQP) is more often considered. On the other hand, the conventional SID SADP flow may be extended quite naturally to triple patterning, with the second mask dividing the gap into two features.[23]

Grid Routing for Mostly Minimum Pitch SADP and SAQP[edit]

SID SADP with grid routing. The dark blue spacer separates the metal wires without cuts.

Toshiba had proposed the grid routing approach for layouts with mostly consistent pitch, this pitch requiring the spacer-based multi-patterning.[14][15][24] The approach allows for 2D layout patterns to be realized even with SADP and SAQP. In particular, for SADP, the cut or trim mask can in principle be eliminated, due to the fact that the spacer does not result in conductive loops. For SAQP, the 2nd spacer, strictly speaking, also defines non-conductive loops, but the remaining unoccupied space between the 2nd spacers represents a conductive feature, which requires trimming. Fortunately, the separation between such trim locations is extended over several feature widths, which simplifies the cutting arrangement. The main concern for mostly minimum pitch in the layout is maximized capacitance, i.e., the minimum pitch results in the maximum capacitance per unit length.

Protrusion Spacer Cutting and Linking Features[edit]

Mandrel or spacer core patterns can be designed to cut their own spacer patterns. A pair of opposing line protrusions can effectively squeeze out any feature in between if a spacer with a thickness exceeding half the distance between the protrusions is deposited, followed by the feature deposition.[25] This is ideal for use in SID SADP schemes. A similar approach is the use of linked features, i.e., narrow constrictions which separate features in spacer patterning without cutting.[26]

The protrusion cutting technique helps reduce the amount of cutting that is needed, and also enables the grid routing method described by Toshiba.[14][15][24] The number of masks used for SAQP is the same as for SADP (1 mandrel/core, 1 trim/cut/block), since only pitch-doubled patterns need cutting. The remaining patterns do not need cutting or trimming, since they are patterned through the same initial exposure.

A similar approach to protrusion cutting is the concept of the linking feature.[27] The linking feature is a narrow constriction which separates features when the sidewall spacer is deposited and patterned. Line jogs, possibly track changing, are necessary to establish the linking feature.

Complementary polarity exposures[edit]

The method of complementary exposures proposed in 2012[28] is another way of reducing mask exposures for multiple patterning. Instead of multiple mask exposures for individual vias, cuts or blocks, two exposures of opposing or complementary polarity are used, so that one exposure removes portions of the previous exposure pattern.

Cut Selection Layer[edit]

The cut pattern may also be generated by spacer patterning with pattern trimming/cutting,[28] rather than by direct exposure. The key benefit is that the cut pattern will not suffer from CD errors associated with the exposure process, such as dose error, focus error, etc. As one or two masks are required to cut a spacer loop, the total number of masks required would be 3 to 4: 1 mask for the line grid, 1 mask for the cutting spacer, 1-2 masks for the cutting of the spacer itself.

EUV vs. Multiple Patterning[edit]

The cost of a single EUV mask exposure is more than 3x that of an immersion mask exposure, from the relative scanner throughput consideration (275 WPH vs. 85 WPH); the deposition and etch costs are relatively much lower. Higher doses to reduce shot noise would increase the cost of EUV dramatically. Other considerations, related to defect management, also bring up the cost of EUV mask exposure further. The use of EUV for cutting exposures is also problematic for feature sizes relevant to 7 nm node and below, as such features are also aggravated by the shot noise issue.[29] EUV 2D patterning is limited to >32 nm pitch.[30] For 16-18 nm half-pitch, the horizontal-vertical bias is over 3 nm, close to a node difference.[31][32] Consequently, EUV would require double patterning for its introduction at 7 nm node below 20 nm half-pitch[33]

EUV beyond single patterning[edit]

EUV imaging quality as a single bidirectional exposure was found to be severely impacted by several factors such as defocus effect on pattern shift, differing best focus conditions for different features, horizontal vs. vertical asymmetry, tip-to-tip distance, and exposure latitude, which all need to be simultaneously optimized. It was found that for 40 nm pitch and 32 nm pitch, the quality as determined by the normalized image log slope was insufficient (NILS<2); only 36 nm pitch was barely satisfactory for bidirectional single exposure.[34] A bidirectional 7 nm node metal layer containing both 36 nm and 48 nm pitch lines, for example, would require double patterning to cover the 48 nm pitch separately (see table below). Furthermore, with no pellicle for EUV in its current state,[35] a cost-reduced SATP or SAQP is expected to be put in place; SAQP is already in use for NAND flash. SAQP is also able to be used from 18 to 12 nm half-pitch, while EUV cannot address the 12 nm half-pitch.

Pitch (nm) Normalized Image Log Slope w/SMO[34] EUV Single Exposure/Double Patterning*
32 1.95 Double Patterning
36 2.15 Single Exposure
40 1.85 Double Patterning
44 1.55 Double Patterning
48 1.35 Double Patterning

* NILS<2.0 is not satisfactory for single exposure

At the 2016 EUVL Workshop, ASML reported that the 0.33 NA NXE EUV tools would not be capable of standard single exposure patterning for the 11-13 nm half-pitch expected at the 5 nm node.[36] A higher NA of 0.55 would allow single exposure EUV patterning of fields which are half the 26 mm x 33 mm standard field size.[36] However, some products, such as NVIDIA's Pascal Tesla P100,[37] will be bisected by the half-field size, and therefore require stitching of two separate exposures.[38] In any case, two half-field scans consume twice as much acceleration/deceleration overhead as a single full-field scan.[36][39]

The existing 0.33 NA EUV tools are challenged below 16 nm half-pitch resolution.[30] Tip-to-tip gaps are problematic for 16 nm dimensions.[40] Hence more than a single EUV exposure would be needed at a minimum for the 7 nm and 5 nm nodes.

Directed Self-Assembly[edit]

The number of masks may be reduced with the use of directed self-assembly (DSA) due to the provision of gridded cuts all at once within a printed area, which can then be selected with a final exposure.[41][42] Alternatively, the cut pattern itself may be generated as a DSA step.[43]

Much progress had been reported on the use of PMMA-PS block copolymers to define sub-20 nm patterns by means of self-assembly, guided by surface topography (graphoepitaxy) and/or surface chemical patterning (chemoepitaxy).[44] The key benefit is the relatively simple processing, compared to multiple exposures or multiple depositions and etching. The main drawback of this technique is the relatively limited range of feature sizes and duty cycles for a given process formulation. Typical applications have been regular lines and spaces as well as arrays of closely packed holes or cylinders.[45] However, random, aperiodic patterns may also be generated using carefully defined guiding patterns.[46]

The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter.[47] A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)−1/2, where a is the statistical polymer chain length.[48] Moreover, χN > 10.5 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π2)1/3aN2/3χ1/6. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.

Cut Redistribution[edit]

Cut redistribution. Redistribution of cuts can reduce the number of required cut masks.

The number of cut masks can also be reduced by allowed redistribution of cuts.[49] Such redistribution also goes well with the implementation of directed self-assembly, described above.

Specific Implementations for Contact/Via Patterns[edit]

Self-Aligned Via[edit]

Since 32 nm node, Intel has applied the above-mentioned self-aligned via approach, which allows two vias separated by a small enough pitch (112.5 nm for Intel 32 nm metal)[50] to be patterned with one resist opening instead of two separate ones.[13] If the vias were separated by less than the single exposure pitch resolution limit, the minimum required number of masks would be reduced, as two separate masks for the originally separated via pair can now be replaced by a single mask for the same pair.

Merged hole separation by etch shrink[edit]

Tokyo Electron Ltd (TEL) was able to resolve two merged contact holes by applying an etch shrink.[51] 31-32 nm contact half-pitch was achieved through this method.[52]

2D SID Spacer Patterning[edit]

The use of SID may be applied to 2D arrays, by iteratively adding features equidistant from the previously present features, doubling the density with each iteration.[53]

Triangular Spacer (Honeycomb Structure) Patterning[edit]

Samsung recently demonstrated DRAM patterning using a honeycomb structure (HCS) suitable for 20 nm and beyond.[54] Each iteration of spacer patterning triples the density, effectively reducing 2D pitch by a factor of sqrt(3).

Multipatterning Implementations[edit]

Reduced capacitance, reduced mask count. A metal layout with reduced capacitance also allows fewer masks, as wider portions are effectively removed without repeated litho-exposure steps (LELE..), leaving less area at minimum pitch (maximum capacitance per unit length).

Memory patterns are already patterned by quadruple patterning for NAND[55] and crossed quadruple/double patterning for DRAM.[56] These patterning techniques are self-aligned and do not require custom cutting or trim masks. For 2x-nm DRAM and flash, double patterning techniques should be sufficient.

Current EUV throughput is still more than 3x slower than 193 nm immersion lithography, thus allowing the latter to be extended by multiple patterning. Furthermore, the lack of an EUV pellicle is also prohibitive.

As of 2016, Intel was using SADP for its 10 nm node;[57] however, as of 2017, the 36 nm minimum metal pitch is now being achieved by SAQP.[58] Intel is using triple patterning for some critical layers at its 14 nm node,[59] which is the LELELE approach.[60] Triple patterning is already demonstrated in 10 nm tapeout,[61] and is already an integral part of Samsung's 10 nm process.[62] TSMC is deploying 7 nm in 2017 with multiple patterning;[63] specifically, pitch-splitting, down to 40 nm pitch.[64] Beyond the 5 nm node, multiple patterning, even with EUV assistance, would be economically challenging, since the departure from EUV single exposure would drive up the cost even higher. However, at least down to 12 nm half-pitch, LELE followed by SADP (SID) appears to be a promising approach, using only two masks, and also using the most mature double patterning techniques, LELE and SADP.[65]

Patterning Costs[edit]

Patterning Method Normalized Wafer Cost
193i SE 1
193i LELE 2.5
193i LELELE 3.5
193i SADP 2
193i SAQP 3
EUV SE 4
EUV SADP 6

Ref.: A. Raley et al., Proc. SPIE 9782, 97820F (2016).

Compared to 193i SADP, EUV SADP cost is dominated by the EUV tool exposure, while the 193i SAQP cost difference is from the added depositions and etches. The processing cost and yield loss at a lithographic tool is expected to be highest in the whole integrated process flow due to the need to move the wafer to specific locations at high speed. EUV further suffers from the shot noise limit, which forces the dose to increase going for successive nodes.[66] On the other hand, depositions and etches process entire wafers at once, without the need for wafer stage motion in the process chamber. In fact, multiple layers may be added under the resist layer for anti-reflection or etch hard-mask purposes, just for conventional single exposure.

Multi-Patterning Practices[edit]

Multipatterning for advanced nodes is already underway. There are two styles being used. Pitch splitting such as LELELE triple patterning is preferred for bidirectional layouts, but is harder to scale. Spacer-based patterning makes use of 1D-type layouts, but requires additional masks for cutting. Cutting lines to form irregular patterns uses the maximum number of masks. However, minimum pitch lines with dense cut locations contribute to higher capacitance by adding more locations and more area of minimum spacing.[67] 2D patterning is generally preferred, but requires sufficient exposed feature pitch, followed by sufficient splitting or division of the pitch. On the other hand, LELE, LELELE, and SADP (SID) can avoid line cuts, while SATP or SAQP with grid routing can minimize line cuts.

EUV may prove too costly to implement against the already established LELELE triple patterning, or the immersion-based combination of mature double patterning techniques LELE+SADP [65] or the implementation of SAQP, which is twice applied SADP, especially the SID form of SADP,[14] with LELE and SID SADP already established for 32 nm and 24 nm half-pitch, respectively.

Company Logic Process Minimum Metal Pitch (MMP) Contacted Gate Pitch (CGP) MMP*CGP CGP:MMP ratio Most Aggressive Technique Production Start
Intel 10nm 36 nm[58] 54 nm[58] 1944 nm2 1.5 SAQP[58][68] end of 2017[69]
TSMC 7nm 40 nm[64] 57 nm[70] 2280 nm2 1.425 LELELE[71] early 2017[72]
Samsung 10LPE 48 nm[73] 64 nm[73] 3072 nm2 1.33 LELELE[62] end of 2016[62]
GlobalFoundries 7LP 40 nm[70] 56 nm[70] 2240 nm2 1.4 LELELE,[74] SADP[70] end of 2018[74]

From a lithographic quality point of view, pitch quartering with 193 nm immersion is better than EUV single exposure. For example, 18 nm half-pitch with 0.33 NA EUV has k1=0.44, while 4x18=72 nm half-pitch with 1.35 NA immersion gives k1=0.50. The ≈14% advantage is always maintained across target pitch. The difficulty increases faster as k1 drops below 0.35. On the other hand, multiple passes would present another difficulty for quadruple patterning. Properly shaping the mandrel is not trivial.[75] Long lines running in one direction require the most cuts; a cut exposure and mask is needed for every path turn. In contrast, spacer patterns with path turns already included do not require cutting if they are used for encapsulating metal.[14]

Triple patterning for 7nm node. Triple patterning may be used for 1D metal layouts with 25-40 nm minimum pitch range.

As the number of masks for a given layer increases, the cost for patterning that layer also increases. It is especially severe when a layer previously requiring only one mask now requires two masks; in this case the cost may roughly be expected to be doubled. On the other hand, the reduced device area from the reduced pitch allows the cost per device to be reduced. The larger pitch reduction allows a larger reduction of cost per device, which counters the effect of increasing mask count.

IMEC has recently studied 7nm scenarios where the pitch in one direction, usually the gate pitch, is larger than the pitch in the perpendicular direction, usually the minimum metal pitch. Such scenarios are advantageous in preventing aggressive increases in mask count when the larger pitch requires SADP instead of SAQP.

Mask Costs[edit]

The mask cost strongly benefits from the use of multiple patterning. The EUV single exposure mask has smaller features which take much longer to write than the immersion mask. Even though mask features are 4x larger than wafer features, the number of shots is exponentially increased for much smaller features. Furthermore, the sub-100 nm features on the mask are also much harder to pattern, with absorber heights ≈70 nm.[76]

Wafer Productivity[edit]

Tool EUV EUV Immersion Immersion
WPH (wafers per hour) 85 85 275 275
# tools 6 6 24[77] 24
uptime 70% 70% 90% 90%
# passes 1 2 2 4
WPM (wafers per month) 257,040 128,520 2,138,400 1,069,200
normalized WPM 1 0.5 8 4

Note: WPM = WPH * # tools * uptime / # passes * 24 hrs/day * 30 days/month. Normalized WPM = WPM/(WPM for EUV 1 pass)

Multiple patterning with immersion scanners can be expected to have higher wafer productivity than EUV, even with as many as 4 passes per layer, due to faster wafer exposure throughput (WPH), a larger number of tools being available, and higher uptime.

Multiple Patterning Specific Issues[edit]

Issue LELE LELELE SID SADP SAQP
Overlay between 1st and 2nd exposures, especially where stitching among all three exposures, especially where stitching between core and cut exposures between core and cut exposures
Exposed feature width (1) 1st exposure (2) 2nd exposure (1) 1st exposure (2) 2nd exposure (3) 3rd exposure core feature (1) core feature (2) cut shape
Feature slimming target width 1/4 exposure pitch 1/6 exposure pitch 1/4 core pitch 1/8 core pitch
Spacer width N/A N/A 1 spacer (1) 1st spacer (2) 2nd spacer

Multiple patterning entails the use of many processing steps to form a patterned layer, where conventionally only one lithographic exposure, one deposition sequence and one etch sequence would be sufficient. Consequently, there are more sources of variations and possible yield loss in multiple patterning. Where more than one exposure is involved, e.g., LELE or cut exposures for SAQP, the alignment between the exposures must be sufficiently tight. Current overlay capabilities are ≈0.6 nm for exposures of equal density (e.g., LELE) and ≈2.0 nm for dense lines vs. cuts/vias (e.g., SADP or SAQP) on dedicated or matched tools.[78] In addition, each exposure must still meet specified width targets. Where spacers are involved, the width of the spacer is dependent on the initial deposition as well as the subsequent etching duration. Where more than one spacer is involved, each spacer may introduce its own width variation.

Industrial Adoption[edit]

7.5-track AOI cell using bidirectional metal. A bidirectional metal layout likely requires three masks (triple patterning), but replaces two orthogonally oriented unidirectional metal layers, which each require two masks, as well as the via layer in between.
Low-height (6-track) AOI metal layers. Reduced height and regularity simplifies the double patterning.
20 nm DRAM 6F2 layout. Due to the layout cut regularity and spacing, only one cut mask (dashed circles) is needed.

10nm FinFETs[edit]

Samsung announced mass production of 10 nm FinFETs in October 2016, featuring triple patterning.[79] Samsung also has developed self-aligned triple patterning (US Patent 9412604). Intel's 10 nm process is comparable density to 7 nm at the three main foundries (TSMC, Samsung, GlobalFoundries).

Low-height 7nm NAND gate cell layout. Low height cells using fewer metal tracks can also be made SAQP-friendly using local regularity.

7nm and 5nm FinFETs[edit]

Self-aligned quadruple patterning is already the established process to be used for patterning fins for 7 nm and 5 nm FinFETs.[80] With SAQP, each patterning step gives a critical dimension uniformity (CDU) value in the sub-nanometer range (3 sigma). Among the four logic/foundry manufacturers, only Intel is applying SAQP to the metal layers, as of 2017.[68] GlobalFoundries has hinted at use of triple patterning.[74]

Reduced cell heights (fewer tracks per cell)[edit]

Recent advances in design-technology co-optimization have led to SAQP-friendly layouts, which do not lead to dramatic mask count increases.[81] Such advances also include reductions of cell height through the use of fewer metal tracks within the cell.[82] The new cell designs result in fewer cut locations and via connections within the cell, while reducing cell area. Essentially, the SAQP metal layers are horizontal lines with at most one connection in the middle of the cell, so that only one block/cut mask is needed without changing lithography tool. Likewise, only diagonally adjacent vias are placed on different masks; vias for every other vertical metal line (corresponding to two gate pitches) may be placed on the same mask.

7nm FinFET SRAM Metal1 connections. Black: V0, Blue: V1, Green outline: M1. Each layer may be split into two (left/right and center) exposures.

DRAM[edit]

Like NAND Flash, DRAM has also made regular use of multiple patterning. Even though the active areas form a two-dimensional array, one cut mask is sufficient for 20 nm.[83] Furthermore, the cut mask may be simultaneously used for patterning the periphery, and thus would not count as an extra mask.[84] However, for 14-18 nm, one additional cut mask would be necessary for dividing the active areas. Samsung has already started manufacturing the 18 nm DRAM.[85]

NAND Flash[edit]

Multiple patterning is routinely used for NAND Flash memory manufacturing. 14 nm is the smallest dimension achieved in 2016.[86] 3D NAND Flash also includes SADP.[87]

Another cost perspective comes from comparing patterning with multiple spacers vs. 3D NAND Flash fabrication, which requires at least 64 distinct layer depositions and etches of those same layers.[88] 16 nm planar NAND requires SAQP (2x SADP) and was the cheapest memory product offered in 2016.[89] However, in 2017, 3D NAND is expected to become cheaper, per bit, as SADP is used to pattern more layers at once.

Advanced Multi-Patterning[edit]

For 20 nm pitch and below, more advanced multiple patterning, such as self-aligned sextuple patterning (SASP),[90] is being considered; alternatively, 20-40 nm pitch SAQP layers using immersion lithography may be converted to SASP layers using dry ArF lithography.

References[edit]

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  2. ^ http://www.eetimes.com/document.asp?doc_id=1327919 EUV 5nm test
  3. ^ Double patterning HSQ processes of zone plates for 10 nm diffraction limited performance
  4. ^ H. Duan, et al., JVST B8, c6c58 (2010).
  5. ^ IMEC double patterning
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