Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the upcoming 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.
Although EUV has been projected to be the next-generation lithography of choice, it would still require more than one lithographic exposure, due to the foreseen need to first print a series of lines and then cut them. It is also likely more than one cut would be needed, even for EUV.
- 1 Pitch Splitting
- 2 Sidewall Image Transfer
- 3 Self-aligned contact/via patterning
- 4 Litho-Etch-Litho-Etch... (LELE...)
- 5 Self-Aligned Double Pattterning (SADP)
- 6 Beyond 193 nm immersion SADP
- 7 Specific Implementations for Contact/Via Patterns
- 8 Industrial adoption
- 9 References
The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called pitch splitting, since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20 nm and 14 nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.
Sidewall Image Transfer
As pitch splitting has become more difficult due to possible differences in feature positions between different exposed parts, sidewall image transfer (SIT) has become more recognized as the necessary approach. The SIT approach typically requires a spacer layer to be formed on an etched feature's sidewall. If this spacer corresponds to a conducting feature, then ultimately it must be cut at no less than two locations to separate the feature into two or more conducting lines as typically expected. On the other hand, if the spacer corresponds to a dielectric feature, cutting would not be necessary. The prediction of how many cuts would be needed for advanced logic patterns has been a large technical challenge. Many approaches for spacer patterning have been published (some listed below), all targeting the improved management (and reduction) of the cuts.
Self-aligned contact/via patterning
Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells and has been extended to patterning of active areas (see "Crossed self-aligned patterning" below). It is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias.
A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.
A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography .
This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration.
A concern with the use of this approach is the discrepancy and delay between the second photoresist pattern and the first hardmask pattern, resulting in an additional source of variation.
A variation on this approach which eliminates the first hardmask etch is resist freezing, which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method, where the freezing is accomplished by surface hardening of the first resist layer.
Self-Aligned Double Pattterning (SADP)
In spacer patterning, a spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. This is commonly referred to as Self-Aligned Doubled Patterning (SADP). The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.
As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness.
The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other. Any misalignment of masks or excursion in pre-patterned feature critical dimension (CD) will cause the pitch between features to alternate, a phenomenon known as pitch walking.
The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned.
Spacer-is-Dielectric (SID) SADP
In self-aligned double patterning (SADP), the number of cut/block masks may be reduced or even eliminated in dense patches when the spacer is used to directly pattern inter-metal dielectric instead of metal features. The reason is the cut/block locations in the core/mandrel features are already patterned in the first mask.
Beyond 193 nm immersion SADP
There have been numerous concerns that multiple patterning diminishes or even reverses the node-to-node cost reduction expected with Moore's Law. EUV is more expensive than three 193i exposures (i.e., LELELE), considering the throughput. Moreover, EUV is more liable to print smaller mask defects not resolvable by 193i.
Self-Aligned Triple Patterning (SATP)
Self-aligned triple patterning has been considered as a promising successor to SADP, due to its introduction of a second spacer offering additional 2D patterning flexibility and higher density. A total of two masks (mandrel and trim) is sufficient for this approach. The only added cost relative to SADP is that of depositing and etching the second spacer. The main disadvantage of SATP succeeding SATP is that it would only be usable for one node. For this reason, self-aligned quadruple patterning (SAQP) is more often considered.
SAQP Grid Routing
Currently, the smallest number of masks for SAQP may be achieved by the grid routing method first described by Toshiba. The number of masks used is the same as for SADP (1 mandrel/core, 1 trim/cut/block), since only SADP loop patterns need cutting. The remaining patterns do not need cutting or trimming, since they are patterned through the same initial exposure.
EUV vs. Multiple Patterning
Beyond 18 nm half-pitch, with no pellicle for EUV in its current state, a cost-reduced SATP or SAQP is expected to be put in place; SAQP is already in use for NAND flash. SAQP is also able to be used from 18 to 12 nm half-pitch, while EUV cannot address the 12 nm half-pitch.
At the 2016 EUVL Workshop, ASML reported that the 0.33 NA NXE EUV tools would not be capable of standard single exposure patterning for the 11-13 nm half-pitch expected at the 5 nm node. A higher NA of 0.55 would allow single exposure EUV patterning of fields which are half the 26 mm x 33 mm standard field size. However, some products, such as NVIDIA's Pascal Tesla P100, will be bisected by the half-field size, and therefore require stitching of two separate exposures. In any case, two half-field scans consume twice as much acceleration/deceleration overhead as a single full-field scan.
The existing 0.33 NA EUV tools are challenged below16 nm half-pitch resolution, hence more than a single EUV exposure would be needed at a minimum for the 7nm and 5nm nodes.
The number of masks may be reduced with the use of directed self-assembly (DSA) due to the provision of gridded cuts all at once within a printed area, which can then be selected with a final exposure. Alternatively, the cut pattern itself may be generated as a DSA step.
As of 2010, much progress was reported on the use of PMMA-PS block copolymers to define sub-20 nm patterns by means of self-assembly, guided by surface topography (graphoepitaxy) and/or surface chemical patterning (chemoepitaxy). The key benefit is the relatively simple processing, compared to multiple exposures or multiple depositions and etching. The main drawback of this technique is the relatively limited range of feature sizes and duty cycles for a given process formulation. Nevertheless, the timing for sub-20 nm node ~2013 is currently being targeted. Typical applications have been regular lines and spaces as well as arrays of closely packed holes or cylinders. However, random, aperiodic patterns may also be generated using carefully defined guiding patterns.
The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter. A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)−1/2, where a is the statistical polymer chain length. Moreover, χN>>10 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π2)1/3aN2/3χ1/6. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.
Specific Implementations for Contact/Via Patterns
Merged hole separation by etch shrink
2D SID Spacer Patterning
The use of SID may be applied to 2D arrays, by iteratively adding features equidistant from the previously present features, doubling the density with each iteration.
Triangular Spacer (Honeycomb Structure) Patterning
Samsung recently demonstrated DRAM patterning using a honeycomb structure (HCS) suitable for 20 nm and beyond. Each iteration of spacer patterning triples the density, effectively reducing 2D pitch by a factor of sqrt(3).
Memory patterns are already patterned by quadruple patterning for NAND and crossed quadruple/double patterning for DRAM. These patterning techniques are self-aligned and do not require custom cutting or trim masks.
Current EUV throughput is still more than 3x slower than 193 nm immersion lithography, thus allowing the latter to be extended by multiple patterning. Furthermore, the lack of an EUV pellicle is also prohibitive.
As of 2016, Intel is using SADP for its 10 nm node. Intel is using triple patterning for some critical layers at its 14nm node, which is the LELELE approach. Triple patterning is already demonstrated in 10nm tapeout. TSMC is deploying 7 nm in 2017 with multiple patterning. Beyond the 5nm node, multiple patterning, even with EUV assistance, would be economically challenging, since the departure from EUV single exposure would drive up the cost even higher. However, at least down to 12 nm half-pitch, LELE followed by SADP (SID) appears to be the most promising approach, using only two masks, and also using the most mature double patterning techniques, LELE and SADP.
|Patterning Method||Normalized Wafer Cost (Ref. 1)||Normalized Wafer Cost (Ref. 2)|
Refs.: (1) L. Liebmann, A. Chu and P. Gutwin, Proc. SPIE 9427, 942702 (2015); (2) A. Raley et al., Proc. SPIE 9782, 97820F (2016).
2D Multi-Patterning Options
Cutting lines to form irregular patterns uses the maximum number of masks. 2D patterning is generally preferred, but requires sufficient exposed feature pitch, followed by sufficient splitting or division of the pitch. On the other hand, LELE, LELELE, and SADP (SID) can avoid line cuts, while SATP or SAQP with grid routing can minimize line cuts. EUV 2D patterning is limited to >32 nm pitch. Consequently, EUV would require double patterning for its introduction at or beyond 7nm; this may prove too costly to implement against the immersion-based combination of mature double patterning techniques LELE+SADP, especially the SID form of SADP,with LELE and SID SADP already established for 14nm and 10nm, respectively.
|14nm||32 nm||LELE (128 nm pitch lithography)||(SE - skipped)|
|10nm||22-24 nm||LELELE or SADP (SID) (mandrel pitch = 92-96 nm)||(SE - skipped)|
|7nm||16 nm||LELE+SADP (SID) or SAQP (128 nm pitch lithography)||LELE|
|5nm||11-12 nm||LELE+SADP (SID) or SAQP (88-96 nm pitch lithography)||LELELE or SADP (SID) (mandrel pitch = 48 nm) or High NA x 2 Fields|
Notes: SE=Single Exposure (conventional lithography); LELE=Litho-(followed by)Etch 2 times; LELELE=Litho-(followed by)Etch 3 times;SADP=Self-Aligned (Spacer) Double Patterning; SID = Spacer-Is-Dielectric; SATP=Self-Aligned (Spacer) Triple Patterning; SAQP=Self-Aligned (Spacer) Quadruple Patterning
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