Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected number of features. The resolution of a photoresist pattern begins to blur at around 45 nm half-pitch. For the semiconductor industry, therefore, double patterning was introduced for the 32 nm half-pitch node and below, mainly using state-of-the-art 193 nm immersion lithography tools.
There are several types of double patterning. In combination, these may be used for multiple patterning.
- 1 Dual-tone photoresist
- 2 Dual-Tone Development
- 3 Self-aligned spacer
- 4 Double/Multiple exposure
- 5 Double Expose, Double Etch (mesas)
- 6 Double Expose, Double Etch (trenches)
- 7 Directed self-assembly (DSA)
- 8 Photoresist Bilayer
- 9 Beyond Double Patterning
- 10 2D layout considerations
- 11 Implementations
- 12 Industrial adoption
- 13 References
Dual-tone photoresists have been developed years ago, allowing the printing of two lines in a single exposure imaging of a single line. Early demonstrations relied on crosslinking of the highest dose regions, rendering them insoluble in developer, while the lowest dose regions were normally insoluble already. Alternatively, a photobase generator may generate acid quenchers at high doses; the acid quenching counters their ability to render the photoresist soluble. The simplicity and cost-effectiveness of this approach make it compelling as a method of extending current photolithographic capability. However, due to its inherent edge-printing characteristic, loops will generally be formed, which will need to be addressed by other process steps. In addition, the expected acid or base diffusion may limit the resolution of this technique.
Dual-tone development, such as Fujifilm's double development process, is similar to the dual-tone photoresist technique above in that it doubles features without additional exposure. Instead the photoresist is developed twice; the first time by conventional developer which removes the high exposure dose areas, the second time by a different organic solvent which removes the unexposed or lowest exposure dose areas. This leaves the intermediate dose areas (normally defining the two feature edges) standing. A key challenge is to not only show successful positive and negative tone development process windows, but also to ensure the windows overlap sufficiently. Up to now, the successful overlap has only been shown in simulations rather than experimentally.
A spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. This is commonly referred to as Self-Aligned Doubled Patterning (SADP). The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.
The spacer approach is unique in that with one lithographic exposure, the pitch can be halved indefinitely with a succession of spacer formation and pattern transfer processes. For example, two iterations of SADP leads to quartering of the pitch or quadrupling of features within the original pitch. Hence, this is often referred to as Self-Aligned Quadruple Patterning (SAQP). This conveniently avoids the serious issue of overlay between successive exposures. The spacer lithography technique has most frequently been applied in patterning fins for FinFETs.
As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness.
The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other.
The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned.
Double exposure is a sequence of two separate exposures of the same photoresist layer using two different photomasks. This technique is commonly used for patterns in the same layer which look very different or have incompatible densities or pitches. In one important case, the two exposures may each consist of lines which are oriented in one or the other of two usually perpendicular directions. Each orientation uses a corresponding dipole illumination. This allows the decomposition of two-dimensional patterns into two one-dimensional patterns which are easier to print. This is the basis of double-dipole lithography (DDL) technology from Brion Technologies, a subsidiary of ASML. The sum of the exposures cannot improve the minimum resolution limit unless the photoresist response is not a simple addition of the two exposures. The double exposure technique allows manufacturability of minimum pitch features in a layout that may contain a variety of features. The 65 nm node saw the introduction of alternating phase-shift masks in manufacturing. This technology is typically a double exposure approach. As long as double exposure can be used effectively and is kept within alignment tolerances, it is the preferred patterning approach since it does not require additional follow-up process steps.
Direct-write electron-beam lithography is inherently a multiple exposure technique, as the beam is shaped and projected onto the resist at multiple locations.
Double Expose, Double Etch (mesas)
This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration.
A concern with the use of this approach is the discrepancy and delay between the second photoresist pattern and the first hardmask pattern, resulting in an additional source of variation.
A variation on this approach which eliminates the first hardmask etch is resist freezing, which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method, where the freezing is accomplished by surface hardening of the first resist layer.
Double Expose, Double Etch (trenches)
A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.
A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography .
As with the double-expose, double-etch mesas approach, any discrepancy among the different interleaved patterns would be a source of feature-to-feature variation.
Directed self-assembly (DSA)
As of 2010, much progress was reported on the use of PMMA-PS block copolymers to define sub-20 nm patterns by means of self-assembly, guided by surface topography (graphoepitaxy) and/or surface chemical patterning (chemoepitaxy). The key benefit is the relatively simple processing, compared to multiple exposures or multiple depositions and etching. The main drawback of this technique is the relatively limited range of feature sizes and duty cycles for a given process formulation. Nevertheless, the timing for sub-20 nm node ~2013 is currently being targeted. Typical applications have been regular lines and spaces as well as arrays of closely packed holes or cylinders. However, random, aperiodic patterns may also be generated using carefully defined guiding patterns.
The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter. A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)−1/2, where a is the statistical polymer chain length. Moreover, χN>>10 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π2)1/3aN2/3χ1/6. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.
SMIC recently developed a double patterning method where a negative-tone developed photoresist is coated over a positive-tone developed photoresist. The two photoresists respond to different dose thresholds, and furthermore, after the upper photoresist is negatively developed, the lower photoresist is etched using the upper photoresist as etch mask. The lower photoresist is subsequently positively developed. This results in a double-patterned structure similar to the spacer patterning method but not requiring the spacer deposition. It is also a single exposure technique, which allows additional cost reduction.
Beyond Double Patterning
The extrapolation of double patterning to multiple patterning has been contemplated, but the issue of cost control is still on the minds of many[who?]. While the benefits of multiple patterning in terms of resolution, depth of focus and lithographic defect sensitivity are understood, there is added burden to control the process budget increase and maintain good yield.
Beyond double (2X) patterning, the most frequently published multiple patterning methodology is the repeated spacer approach, which can be practiced in many forms. A multilayer-on-topography spacer-type approach also offers some flexibility. It is also possible to additively combine two or more of the above approaches. For example, a dual-tone photoresist with pitch-halved acid profile, plus dual-tone development that dissolves the highest and lowest acid concentrations, combined with a spacer process, would result in 8x pitch resolution enhancement,e.g., 40 nm half-pitch reduced to 5 nm half-pitch. Subsequently repeating the spacer process would give 16 x pitch resolution improvement, e.g., 40 nm half-pitch reduced to 2.5 nm half-pitch. The European LENS (Lithography Enhancement Towards Nano Scale) project is targeted toward implementation of both double exposure (resist freezing) and spacer-based process, in principle enabling two ways of patterning for ~20 nm design rules with current lithography tools, already tailored for double patterning or ~10 nm design rules in combination. With successful dual-tone development of a dual-tone photoresist, 2.5 nm design rules can be imagined.
Intel used several spacer deposition/etch/clean steps to demonstrate spacers spaced apart by ~26 nm. It represents a reduction of the original patterned pitch by a factor of ~1/4 and indicates that wavelength and optics no longer purely determine the lithographic resolution.
At the 2010 Flash Memory Summit, it was projected that immersion lithography with multiple patterning would be used to scale NAND Flash to below 20 nm within a few years.
2D layout considerations
For 2D patterns the density increase is very dependent on the nature of the pattern. For instance, contact arrays have optimal packing density as rectangular arrays for double patterning but as hexagonal close packed arrays for triple patterning – achieving a close to 2 and 3 times area improvement respectively. Regular array layouts such as used for DRAM could use cross self-aligned spacer patterning. For 2D layouts double patterning compliance errors occur when there are odd cycles of minimum spaces. This can be resolved by relaxing one of these spaces to a distance where both features can be patterned in the same imaging step. Triple patterning is compliant with odd cycles but in turn is non-compliant for two facing pairs of line-ends where the corner to corner space is below the single patterning distance. This in turn is compliant under quadruple patterning. The improvement in density with the use of multiple patterning schemes is thus highly dependent on the pattern. Often simple redesigns or relaxation of dimensions in one direction can avoid the expense of going to more complex and expensive multiple patterning processes.
Below 40 nm half-pitch, the continued use of 193 nm immersion lithography entails an increasing number of exposures, even for regular array patterns. Only purely one-dimensional line patterns will not need to increase the number of exposures. However, the number of exposures for regularly arranged two-dimensional layouts can be minimized. In fact, as long as the number of exposures is not doubled in advancing to the next node, as density is doubled, additional exposures do not pose a prohibitive cost penalty.
In the original spacer-based technique, the spacers defined conducting features which needed to be cut to avoid forming loops. In the spacer-is-dielectric (SID) approach, the spacers define dielectric spaces between conducting features, and so no longer need cuts. Instead the mandrel definition becomes more strategic in the layout, and there is no longer a preference for 1D line-like features. The SID approach has gained popularity due to its flexibility with minimal additional mask exposures.
Synopsys has begun consideration of triple patterning decomposition of layers which are less easy to split into two patterns, such as contact layers. While only increasing the number of processing steps by 50% (compared to 100% for the insertion of double patterning), triple patterning would enable 16 nm node patterning on a 45 nm node lithography tool. Likewise, quadruple patterning would enable 11 nm node patterning on the same 45 nm node lithography tool, with only 33% additional steps over triple patterning.
Sidewall profile modulation
The Sidewall Profile Inclination Modulation Mask (SPIMM) technique was proposed in 2013 as a means to reduce the number of exposures for spacer-defined or possibly DSA-defined double patterning or multiple patterning even for arbitrary, non-arrayed patterns. A dose gradient, such as from a narrowed space adjacent a feature sidewall, is transferred to form a specific sidewall profile, which allows the deposited spacer patterning to be interrupted locally. A developable BARC process is a suitable opportunity for this approach, due to its reduced exposure contrast.
Due to its rather straightforward application, without the need to change the infrastructure, multiple patterning is not expected to encounter any insurmountable technical or commercialization barriers. Despite the cost and throughput concerns, it has recently received more attention and interest, mainly due to delays in next-generation lithography techniques such as EUVL and nanoimprint lithography.
Multiple patterning can also exploit high-bias processes (for example, photoresist trimming to reduce linewidth, or photoresist reflow to reduce trench width) to substantially eliminate defects sized at around 2x the design pitch or smaller. This is a significant advantage over increasing lithography tool resolution, which exposes the wafer to more defects at the design rule or even smaller.
Self-aligned contact/via patterning
Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells as well as advanced node logic.
Merged hole repair by etch shrink
2D SID Spacer Patterning
The use of SID may be applied to 2D arrays, by iteratively adding features equidistant from the previously present features, doubling the density with each iteration.
Chip stacking of multiple dies
EUV and Electron-beam lithography
At the 2013 EUVL Workshop, it was concluded that even EUV would require double patterning and DSA for continued scaling below 10 nm, extending into multiple patterning for 450 mm usage
As mentioned previously, electron-beam lithography is inherently a multiple exposure technique. However, even electron beam lithography and EUV would eventually require at least two interleaved exposures (due to secondary electron scattering), for instance, in the fabrication of 15 nm half-pitch X-ray zone plates. In fact, double patterning may not even be sufficient for sub-12 nm half-pitch, even with electron beam lithography. In that case, multiple patterning would be necessary.
Tela Innovations, a startup founded in 2005 which has recently garnered significant support and funding, specializes in converting arbitrary layouts into array-like features suitable for double patterning. Tela Innovations achieves this by using gridded layouts.
Intel has been using double patterning in its 45 nm as well as its 65 nm technology. Double patterning is used to square off the ends of the transistor gates. The first mask pattern consists of the gate lines linked at the end. The second mask is a line cutter that separates these into separate gates, using a second photoresist coating. The extra steps for the 45 nm double patterning compared to 65 nm are necessary due to the use of dry instead of immersion lithography.
In September 2009, Intel disclosed that for its 15 nm process, EUV did not appear to be ready in timely fashion. Hence, Intel is preparing to extend 193 nm immersion lithography with double and possibly triple patterning to 15 nm.
For its 11 nm logic node (20-22 nm half-pitch), Intel expects to be able to use quintuple exposure with 193 nm lithography, where one of the exposures is used with spacer patterning for a further pitch division. The remaining four exposures are for cutting the pitch-divided lines. Even with a next-generation lithography like EUVL or maskless direct-write electron-beam lithography, a second exposure is still required for cutting. Referenced to its 32 nm node technology, the density is expected to be enhanced about 8x (three generations of doubling density), but the cost is less than 6x (5 exposures, with one round of spacer patterning).
Intel revealed in 2014 that it is using triple patterning for some layers in its 14 nm node.
At the 2010 Sematech Litho Forum, it was recommended by TI that for the 60 nm routed pitch layers, corresponding to the 22/20 nm node, double patterning "is the only economically feasible solution." Double and triple patterning was considered cost effective for dies with a routed pitch of about 40 nm. For the 14 nm node, triple patterning will be required for the gate, contact, and metal 1 layers. It was claimed that triple patterning at the 44 nm pitch provided a 25% better cost reduction.
NAND Flash Memory Makers
In 2010, IM Flash began producing 20.5 nm NAND Flash, with the combination of 193 nm immersion lithography and double patterning.
Similar to the multiple patterning approach described for Intel's 11 nm process, in actual practice, NAND Flash memory array patterning using the spacer approach would use 3 or more mask exposures. The first mask patterns the array core by defining the spacers, while a second mask is used to crop or trim the spacers to form individual lines. Lastly, additional masks or multiple patterning would be used to pattern peripheral connections, e.g., pads. Three, four, and five masks are required in total for self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and self-aligned octuple patterning (SAOP), respectively. As a result, Flash memory patterning can generally be considered multiple patterning, not just a spacer-based double-patterning technique.
At IEDM 2011, Hynix reported on a 15 nm NAND process, making use of, among other things, quadruple spacer patterning. Sub-20 nm NAND flash is fabricated with use of self-aligned quadruple patterning. Micron has already been producing 16 nm NAND Flash with this technique since 2013.
The cost of multiple mask exposures has always been a major industrial concern. As more and more masks are added, the cost reduction from one technology node to the next would begin to dwindle. On the other hand, low-k1 approaches already can involve the use of double exposure for non-regular 2D patterns, but the industry seems to have bypassed this concern of loss of cost reduction.
Multiple patterning with existing 193 nm immersion lithography has always been the backup lithography technique in the event of EUV being not ready, provided the costs are not prohibitive. Even with EUV availability, it is also likely it would be applied along with 193 nm immersion for a critical layer. For example, up to 4 cut exposures by 193 nm immersion lithography may be replaced by one or two EUV exposures.
A key consideration for the implementation of multiple patterning is the tool throughput. Also relevant is the number of tools available for multiple patterning. Current 193 nm immersion scanner throughput is capable of 250 WPH. EUV has achieved about 42 WPH or 1000 wafers per day, while 193 nm immersion including multiple patterning has shown over 3000 wafers per day. Thus, extending multiple patterning is still a planned option for future nodes.
A recent cost study by IMEC showed that SAQP/LE3 (self-aligned quadruple patterning with 3 cut/via exposures) with a 193 nm immersion tool throughput of 150 WPH would be same cost as 55 WPH EUV single patterning for the 7 nm node. The current immersion and EUV throughputs of 250 WPH and 42 WPH, respectively, therefore make multiple patterning currently the likely approach to be used down to 7 nm, and even beyond with EUV.
Besides the number of masks needed per layer, the total number of masks used for all the layers, or at least the critical layers, must be considered. ASML projects that the number of lithography steps would continue increasing even with the introduction of EUV. The number of masks may be reduced with the use of DSA due to the provision of gridded cuts all at once within a printed area, which can then be selected with a final exposure. Alternatively, the cut pattern itself may be generated as a DSA step.
In 2015, IMEC revealed that 7 nm SRAM scaling can be continued with only two masks (instead of the five originally projected) being added with 193 nm immersion lithography with SADP (i.e., a total of three masks) for the local interconnect layer and with comparable cell area to EUV single patterning (~50% of 10 nm node). The current EUV tools in the field have a numerical aperture (NA) of 0.33 and a resolution of 19 nm half-pitch, which is insufficient for the 7 nm node (16 nm half-pitch). However, the use of a total of three 193 nm immersion lithography masks may be carried over from 10 nm node logic metal layers to 7 nm node logic metal layers.
Cut exposures may also be reduced by the method of complementary exposures. With this method, several exposures expected for self-aligned quadruple patterning may be reduced to two or three.
Spacer-is-dielectric (SID) is a style of SADP which allows additional flexibility of design down to sub-10 nm nodes. The flexibility comes from having the spacer not define the metallic features, since they are normally loops which need to be cut. By having the spacer define dielectric locations, separate line cutting exposures can be minimized, even possibly eliminated with the SPIMM approach described above. Additional resolution is achieved by conversion into the SAQP approach by having the metal-patterning mandrels themselves defined by SADP. A double-patterned metal pattern layout can turn into a quadruple-patterned layout, without additional masks, due to the final spacer loop being dielectric. In this way, the cost effectiveness of multiple patterning even for flexible 2D layouts is improved with the use of (up to) two masks for SAQP down to ~11-12 nm half-pitch. EUV thus far has not shown 2D flexibility for 16 nm half-pitch (7 nm node) and would therefore require the same number of mask exposures as 193 nm immersion in this case. SAQP may be extended to SAOP by applying an additional spacer. The benefit of SID in extending multiple patterning may be generalized, noting that a 2N-patterned metal pattern layout can turn into a 4N-patterned layout, without additional masks, due to the final spacer loop being dielectric.
Intel 10 nm
Intel reported in 2013 that it would be using pitch quartering, i.e., SAQP, for its 10 nm node (15-22 nm half-pitch), instead of EUV. However, Intel's 10 nm introduction has apparently been delayed from 2015 to 2017.
Establishment of triple patterning for 10 nm
Triple patterning is already established for 14 nm and 10 nm nodes. Any self-aligned multiple patterning followed by two trimming or cutting exposures (SAQP-LELE) for 7 nm and 5 nm nodes, effectively extends triple patterning to these nodes. Fewer cuts, e.g., enabled by SID, would offer even more cost-effective scalability. On the other hand, the self-aligned multiple patterning would be defined as quadruple patterning due to pitch-halving necessarily giving way to pitch quartering.
7 nm logic node (and beyond) patterning
Quadruple patterning is expected for the 7 nm node. In the earliest sense, it implied four separate exposures. However, currently, self-aligned quadruple patterning is favored. Such an approach would entail two rounds of spacer deposition and etchback, followed by removal of the spacer supports (mandrels). On the other hand, a ~22 nm minimum pitch (corresponding to 5 nm logic node) contact layer can be patterned by triple patterning with a 1D-type layout and using the hole etch shrink technique mentioned above.
EUV requiring double patterning
- T. Honda et al., J. Microlith., Microfab., Microsyst., Vol. 5, 043004 (2006).
- C. Fonseca et al., Proc. SPIE vol. 7274, 72740I (2009).
- U. S. Patent 6114082.
- S. Song et al., Polymers for Adv. Tech. 9, 326-333 (1998).
- X. Gu et al., J. Photopoly. Sci. & Tech. 22, 773-781 (2009).
- K. Derbyshire, Solid State Technology, March 4, 2008.
- X. Hua et al., J. Vac. Sci. Tech. B, vol. 24, pp. 1850-1858 (2006).
- Y-K Choi et al., J. Phys. Chem. B, vol. 107, pp. 3340-3343 (2003).
- See for example, US Patent 5308741.
- Brion implements ASML' DDL Technology
- A. Tritchkov, S. Jeong, and C. Kenyon, "Lithography Enabling for the 65 nm node gate layer patterning with Alternating PSM," Proc. SPIE vol. 5754, pp.215-225 (2005).
- IMEC double patterning
- S. H. Park et al., Soft Matter, 6, 120-125 (2010).
- Chipmakers Mull Plans to Insert DSA at 14 nm
- C. G. Hardy and C. Tang, J. Polymer Sci. Pt. B: Polymer Phys., vol. 51, pp. 2-15 (2013).
- L-W. Chang et al.IEDM 2010 Technical Digest, 752-755 (2010).
- NIST 2011 report on LER in PS-b-PMMA DSA
- A. N. Semenov, Macromolecules 26, 6617 (1993).
- U.S. Patent 9070557, assigned to SMIC
- A. Carlson and T-J. K. Liu, Proc. SPIE 6924, 69240B (2008).
- B. Degroote et al., Microelec. Eng., 84, 609-618 (2007).
- Y-K. Choi et al., Proc. SPIE 5220, 10 (2003).
- US 6759180
- US 5328810
- US 7919413
- P. Cantu et al., Proc. SPIE 7640, 764022 (2010).
- T. Castenmiller et al., Proc. SPIE 7640, 76401N (2010).
- EETimes: IMFT 25-nm MLC NAND: technology scaling barriers broken, 3/22/2010
- SEMICON West - Lithography Challenges and Solutions
- EETimes "EUV litho keeps progressing, keeps slipping", 6/9/2010.
- G. Tressler (IBM), 2010 Flash Memory Summit[dead link]
- US Patent 9012330, assigned to Nanya Technology.
- B-S Seo et al, "Double Patterning addressing Imaging challenges for near and sub k1=0.25 node layouts", Proc. SPIE, Volume 7379, 73791N (2009).
- Y. Du et al., "Spacer-Is-Dielectric-Compliant Detailed Routing for Self-Aligned Double Patterning Lithography", DAC 2013.
- C. Cork et al., Proc. SPIE, vol. 7028, 702839 (2008).
- F. T. Chen et al., Proc. SPIE vol. 8683, 868311 (2013).
- F. T. Chen et al., J. Micro/Nanolith. MEMS MOEMS 13(1), 011008 (Jan–Mar 2014).
- J. Lowes et al., Proc. SPIE 7639, 76390K (2010).
- T. Katayama et al., Proc. SPIE 5377, 968–973 (2004).
- US Patent 6165880, assigned to TSMC.
- K. Oyama et al., Proc. SPIE 9051, 90510V (2014).
- M. C. Smayling et al., Proc. SPIE 9426, 94261U (2015).
- B. Mebarki et al., U. S. Patent 8,084,310, assigned to Applied Materials.
- Elpida stacks four DDR3 DRAMs
- http://www.euvlitho.com/2013/2013%20EUVL%20Workshop%20Summary.pdf 2013 EUVL Workshop Summary
- E. Anderson and W. Chao, Double exposure makes high-resolution diffractive optics, SPIE Newsroom, 2007.
- W. Chao et al., JVST B 27, 2606-2611 (2009).
- W. Chao et al., Proc. SPIE vol. 6883, 688309 (2008).
- M. D. Levenson, "SPIE: Tela Innovations lays it all out straight", Microlithography World, Feb. 28 2008.
- D. Vogler, Solid State Technology, Intel product launch event yields more insight into its manufacturing strategy
- Intel Technology Journal June 17, 2008
- Intel 45 nm process at IEDM
- Semiconductor International 9/14/2009 Intel Ramping 32 nm Manufacturing in Oregon
- EETimes 9/22/2009 Otellini: Intel to ship more SOCs than PC CPUs -- someday
- Intel to extend ArF lithography to 11 nm
- Intel Opens Door on 7 nm, Foundry
- Focus Shifts to Affordability.
- 25 nm NAND announcement
- C. Bencher, Nanochip Technology Journal, 2007.
- U.S. Patent 7808053.
- J. Yu et al., Proc. SPIE 9052, 90521P (2014).
- IEDM 2011 Press Tip Sheet
- Sidewall spacer quadruple patterning for 15nm half-pitch.
- Complementary Lithography at Insertion and Beyond
- http://www.digitimes.com/news/a20121224PR200.html Samsung delivers 14nm FinFET logic process and design infrastructure
- http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/more-hkmg-hits-the-market-gate-first-and-gate-last/ Chipworks coverage of TSMC 28 nm HKMG process
- http://www.tsmc.com/tsmcdotcom/PRListingNewsAction#do?action=detail&&newsid=2423&&newsdate=2007/12/11 TSMC 32 nm SRAM announcement
- ASML TWINSCAN NXT:1970Ci
- Nikon NSR-S630D
- TSMC runs 1022 wafers per day with EUV
- A. Mallik et al., Proc. SPIE 9048, 90481R (2014).
- M. van den Brink, ASML Investor Day, Nov. 24, 2014.
- Synopsis Presentation at Semicon West 2013
- M. C. Smayling et al., Proc. SPIE 8683, 868305 (2013).
- Z. Xiao et al., Proc. SPIE 8880, 888017-3 (2013).
- S. S. Sakhare et al., SPIE Advanced Lithography 2015, Paper 9427-24 Abstract.
- J. van School et al., Proc. SPIE vol. 9422, 94221F (2015).
- L. Liebmann, A. Chu, and P. Gutwin, Proc. SPIE vol. 9427, 942702 (2015).
- W. Gillijns et al., Proc. SPIE vol. 9427, 942709 (2015).
- F. T. Chen et al., Proc. SPIE vol. 8326, 83262L (2012).
- Y. Ban and D. Z. Pan, J. Micro/Nanolith. MEMS MOEMS 14, 011004 (2015).
- C. Kodama et al., IEEE Trans. CAD Integ. Circ. and Syst., vol. 34, 753 (2015).
- Y. Chen, Q. Cheng and W. Kang, Proc. SPIE 8328, 83280O (2012).
- E. van Setten et al., Proc. SPIE vol. 9231, 923108 (2014).
- A. Pirati et al., Proc. SPIE vol. 9422, 94221P (2015).
- J. Yu et al., Proc. SPIE vol. 9052, 90521P (2014).
- Intel pushes EUV beyond 10 nm
- Intel delays 10 nm to 2017
- Pushing Multiple Patterning in Sub-10nm: Are We Ready?, DAC 2015
- R. Nakayama et al., Proc. SPIE vol. 9658, 96580A (2015).
- ASML - Many ways to shrink (Nov 2014)